公开(公告)号：US5717587A

公开(公告)日：1998-02-10

申请号：US649753

申请日：1996-05-15

申请人： Bryan Black ,  Marvin A. Denman ,  Lee E. Eisen ,  Robert T. Golla ,  Albert J. Loper, Jr. ,  Soummya Mallick ,  Russell Adley Reininger

发明人： Bryan Black ,  Marvin A. Denman ,  Lee E. Eisen ,  Robert T. Golla ,  Albert J. Loper, Jr. ,  Soummya Mallick ,  Russell Adley Reininger

IPC分类号： G06F9/30 ,  G06F9/318 ,  G05B15/00

CPC分类号： G06F9/3017 ,  G06F9/30145

摘要： A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units. Detecting noneffective instructions prior to dispatch reduces the decode logic required within the dispatcher and enhances processor performance.

摘要翻译： 公开了一种用于处理包括具有多个执行单元的处理器的数据处理系统内的指令的方法和系统。 根据本发明的方法，从存储器中检索存储在数据处理系统内的存储器内的多个指令。 解码指令数目中的选择指令，以确定所选择的指令是否由处理器执行时是无效的。 在本发明的优选实施例中，无效指令包括具有无效操作码的指令和不会改变处理器内的任何数据寄存器的值的指令。 响应于确定所选择的指令如果由处理器执行将是无效的，则在将所选择的指令分派到多个执行单元之一之前，所选择的指令被重新编码为指定的指令格式。 在调度之前检测无效指令可减少调度程序中所需的解码逻辑，并提高处理器的性能。

公开(公告)号：US5732235A

公开(公告)日：1998-03-24

申请号：US591291

申请日：1996-01-25

申请人： James Allan Kahle ,  Soummya Mallick ,  Larry Bryce Phillips ,  Russell Adley Reininger

发明人： James Allan Kahle ,  Soummya Mallick ,  Larry Bryce Phillips ,  Russell Adley Reininger

IPC分类号： G06F9/318 ,  G06F9/30

CPC分类号： G06F9/30174 ,  G06F9/3879 ,  G06F9/45504

摘要： A system and method for reducing the cycle time necessary to execute semantic routines in a processor that emulates guest instructions. Each of the semantic routines includes a block of host instructions for performing the function of the corresponding guest instruction, and the last instruction in each of the semantic routines is a branch instruction. The method and system first determines the block length of each of the semantic routines. When a first guest instruction is encountered, the block of instructions in a first semantic routine corresponding to a guest instruction is executed. The block length of first semantic routine is then used to determine when to fetch a second semantic routine without fetching and decoding the branch instruction in the first semantic routine, thereby increasing emulation performance.

摘要翻译： 一种用于减少在模拟客户指令的处理器中执行语义例程所需的周期时间的系统和方法。 每个语义例程包括用于执行相应来宾指令的功能的主机指令块，并且每个语义例程中的最后一条指令是分支指令。 该方法和系统首先确定每个语义例程的块长度。 当遇到第一访客指令时，执行对应于访客指令的第一语义程序中的指令块。 然后，第一语义例程的块长度用于确定何时获取第二语义例程而不在第一语义例程中取出和解码分支指令，从而增加仿真性能。