公开(公告)号：US5717587A

公开(公告)日：1998-02-10

申请号：US649753

申请日：1996-05-15

申请人： Bryan Black ,  Marvin A. Denman ,  Lee E. Eisen ,  Robert T. Golla ,  Albert J. Loper, Jr. ,  Soummya Mallick ,  Russell Adley Reininger

发明人： Bryan Black ,  Marvin A. Denman ,  Lee E. Eisen ,  Robert T. Golla ,  Albert J. Loper, Jr. ,  Soummya Mallick ,  Russell Adley Reininger

IPC分类号： G06F9/30 ,  G06F9/318 ,  G05B15/00

CPC分类号： G06F9/3017 ,  G06F9/30145

摘要： A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units. Detecting noneffective instructions prior to dispatch reduces the decode logic required within the dispatcher and enhances processor performance.

摘要翻译： 公开了一种用于处理包括具有多个执行单元的处理器的数据处理系统内的指令的方法和系统。 根据本发明的方法，从存储器中检索存储在数据处理系统内的存储器内的多个指令。 解码指令数目中的选择指令，以确定所选择的指令是否由处理器执行时是无效的。 在本发明的优选实施例中，无效指令包括具有无效操作码的指令和不会改变处理器内的任何数据寄存器的值的指令。 响应于确定所选择的指令如果由处理器执行将是无效的，则在将所选择的指令分派到多个执行单元之一之前，所选择的指令被重新编码为指定的指令格式。 在调度之前检测无效指令可减少调度程序中所需的解码逻辑，并提高处理器的性能。

公开(公告)号：US5619408A

公开(公告)日：1997-04-08

申请号：US387145

申请日：1995-02-10

申请人： Bryan Black ,  Marvin A. Denman ,  Lee E. Eisen ,  Robert T. Golla ,  Albert J. Loper, Jr. ,  Soummya Mallick ,  Russell A. Reininger

发明人： Bryan Black ,  Marvin A. Denman ,  Lee E. Eisen ,  Robert T. Golla ,  Albert J. Loper, Jr. ,  Soummya Mallick ,  Russell A. Reininger

IPC分类号： G06F9/30 ,  G06F9/318 ,  G05B15/00

CPC分类号： G06F9/3017 ,  G06F9/30145

摘要： A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units. Detecting noneffective instructions prior to dispatch reduces the decode logic required within the dispatcher and enhances processor performance.

摘要翻译： 公开了一种用于处理包括具有多个执行单元的处理器的数据处理系统内的指令的方法和系统。 根据本发明的方法，从存储器中检索存储在数据处理系统内的存储器内的多个指令。 解码指令数目中的选择指令，以确定所选择的指令是否由处理器执行时是无效的。 在本发明的优选实施例中，无效指令包括具有无效操作码的指令和不会改变处理器内的任何数据寄存器的值的指令。 响应于确定所选择的指令如果由处理器执行将是无效的，则在将所选择的指令分派到多个执行单元之一之前，所选择的指令被重新编码为指定的指令格式。 在调度之前检测无效指令可减少调度程序中所需的解码逻辑，并提高处理器的性能。

公开(公告)号：US5809323A

公开(公告)日：1998-09-15

申请号：US530552

申请日：1995-09-19

申请人： Lee E. Eisen ,  Robert T. Golla ,  Soummya Mallick ,  Sung-Ho Park ,  Rajesh B. Patel ,  Michael Putrino

发明人： Lee E. Eisen ,  Robert T. Golla ,  Soummya Mallick ,  Sung-Ho Park ,  Rajesh B. Patel ,  Michael Putrino

IPC分类号： G06F9/302 ,  G06F9/38

CPC分类号： G06F9/3001 ,  G06F9/3836 ,  G06F9/384

摘要： A superscalar processor and method for executing fixed-point instructions within a superscalar processor are disclosed. The superscalar processor has a memory and multiple execution units, including a fixed point execution unit (FXU) and a non-fixed point execution unit (non-FXU). According to the present invention, a set of instructions to be executed are fetched from among a number of instructions stored within memory. A determination is then made if n instructions, the maximum number possible, can be dispatched to the multiple execution units during a first processor cycle if fixed point arithmetic and logical instructions are dispatched only to the FXU. If so, n instructions are dispatched to the multiple execution units for execution. In response to a determination that n instructions cannot be dispatched during the first processor cycle, a determination is made whether a fixed point instruction is available to be dispatched and whether dispatching the fixed point instruction to the non-FXU for execution will result in greater efficiency. In response to a determination that a fixed point instruction is not available to be dispatched or that dispatching the fixed point instruction to the non-FXU will not result in greater efficiency, dispatch of the fixed point instruction is delayed until a second processor cycle. However, in response to a determination that dispatching the fixed point instruction to the non-FXU will result in greater efficiency, the fixed point instruction is dispatched to the non-FXU and executed, thereby improving execution unit utilization.

摘要翻译： 公开了一种用于在超标量处理器内执行定点指令的超标量处理器和方法。 超标量处理器具有存储器和多个执行单元，包括固定点执行单元（FXU）和非固定点执行单元（非FXU）。 根据本发明，从存储在存储器中的多个指令中取出要执行的一组指令。 然后如果将固定点算术和逻辑指令仅发送到FXU，则可以在第一处理器周期期间将n个指令（尽可能最大数）分派到多个执行单元进行确定。 如果是这样，n个指令被分派到多个执行单元执行。 响应于在第一处理器周期期间不能调度n个指令的确定，确定是否可以调度固定点指令，以及是否向非FXU分派定点指令以执行将导致更高的效率 。 响应于确定不能发送固定点指令或者将定点指令分派到非FXU不会导致更高的效率，所以定点指令的调度被延迟到第二处理器周期。 然而，响应于将定点指令发送到非FXU的确定将导致更高的效率，将定点指令分派到非FXU并执行，从而提高执行单元的利用率。

公开(公告)号：US5732235A

公开(公告)日：1998-03-24

申请号：US591291

申请日：1996-01-25

申请人： James Allan Kahle ,  Soummya Mallick ,  Larry Bryce Phillips ,  Russell Adley Reininger

发明人： James Allan Kahle ,  Soummya Mallick ,  Larry Bryce Phillips ,  Russell Adley Reininger

IPC分类号： G06F9/318 ,  G06F9/30

CPC分类号： G06F9/30174 ,  G06F9/3879 ,  G06F9/45504

摘要： A system and method for reducing the cycle time necessary to execute semantic routines in a processor that emulates guest instructions. Each of the semantic routines includes a block of host instructions for performing the function of the corresponding guest instruction, and the last instruction in each of the semantic routines is a branch instruction. The method and system first determines the block length of each of the semantic routines. When a first guest instruction is encountered, the block of instructions in a first semantic routine corresponding to a guest instruction is executed. The block length of first semantic routine is then used to determine when to fetch a second semantic routine without fetching and decoding the branch instruction in the first semantic routine, thereby increasing emulation performance.

摘要翻译： 一种用于减少在模拟客户指令的处理器中执行语义例程所需的周期时间的系统和方法。 每个语义例程包括用于执行相应来宾指令的功能的主机指令块，并且每个语义例程中的最后一条指令是分支指令。 该方法和系统首先确定每个语义例程的块长度。 当遇到第一访客指令时，执行对应于访客指令的第一语义程序中的指令块。 然后，第一语义例程的块长度用于确定何时获取第二语义例程而不在第一语义例程中取出和解码分支指令，从而增加仿真性能。

公开(公告)号：US5897654A

公开(公告)日：1999-04-27

申请号：US881223

申请日：1997-06-24

申请人： Lee E. Eisen ,  Belliappa M. Kuttanna ,  Soummya Mallick ,  Rajesh B. Patel

发明人： Lee E. Eisen ,  Belliappa M. Kuttanna ,  Soummya Mallick ,  Rajesh B. Patel

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0859 ,  G06F12/0862

摘要： A method and system in a data processing system for efficiently interfacing with cache memory by allowing a fetcher to read from cache memory while a plurality of data words or instructions are being loaded into the cache. A request is made by a bus interface unit to load a plurality of instructions or data words into a cache. In response to each individual instruction or data word being loaded into the cache by the bus interface unit, there is an indication that the individual one of said plurality of instructions or data words is valid. Once a desired instruction or data word has an indication that it is valid, the fetcher is allowed to complete a fetch operation prior to all of the instructions or data words being loaded into cache. In one embodiment, a group of invalid tag bits may be utilized to indicate to the fetcher that individual ones of a group of instructions or data words are valid in cache after being written into cache by the bus interface unit.

摘要翻译： 数据处理系统中的一种方法和系统，用于通过在多个数据字或指令被加载到高速缓存中允许读取器从高速缓冲存储器中读取来高效地与高速缓存存储器连接。 总线接口单元请求将多个指令或数据字加载到高速缓存中。 响应于由总线接口单元加载到高速缓存中的每个单独指令或数据字，存在所述多个指令或数据字中的单个指令或数据字有效的指示。 一旦所需的指令或数据字具有有效的指示，则在所有指令或数据字被加载到高速缓存之前，允许提取器完成取指操作。 在一个实施例中，一组无效标签位可以被用于在由总线接口单元写入高速缓存之后向读取器指示一组指令或数据字中的各个有效。

公开(公告)号：US20060294356A1

公开(公告)日：2006-12-28

申请号：US11168757

申请日：2005-06-27

申请人： Santosh Kumar ,  Soummya Mallick ,  Krishnakumar Mani ,  Venkat Raman

发明人： Santosh Kumar ,  Soummya Mallick ,  Krishnakumar Mani ,  Venkat Raman

IPC分类号： G06F9/00

CPC分类号： G06F9/44573

摘要： Apparatuses and methods of an executable-in-place solid-state device are disclosed. In one embodiment, a solid-state device includes a flash memory coupled to a dynamic random access memory, the dynamic random access memory to store at least as much data as the flash memory; and a logic circuit coupled to the flash memory and the dynamic access memory to copy data from the flash memory to the dynamic random access memory on power up of a data processing system coupled to the solid-state device. The logic circuit is to minimize writes to the flash memory by using the dynamic access memory as a working memory during operation of the data processing system, and/or to block at least some sectors of at least one of the flash memory and the dynamic random access memory when the data processing system uses the working memory to conserve power usage of the solid-state device.

摘要翻译： 公开了可执行就地固态设备的装置和方法。 在一个实施例中，固态设备包括耦合到动态随机存取存储器的闪速存储器，动态随机存取存储器至少存储与闪速存储器相同的数据; 以及耦合到闪速存储器和动态访问存储器的逻辑电路，用于在耦合到固态设备的数据处理系统上电时将数据从闪速存储器复制到动态随机存取存储器。 逻辑电路是通过在数据处理系统的操作期间使用动态存取存储器作为工作存储器来最小化对闪速存储器的写入，和/或阻止闪存和动态随机的至少一个的至少一些扇区 当数据处理系统使用工作存储器来节省固态设备的功率使用时，存取存储器。

公开(公告)号：US06212542B1

公开(公告)日：2001-04-03

申请号：US08767487

申请日：1996-12-16

申请人： James A. Kahle ,  Soummya Mallick ,  Robert G. McDonald ,  Edward L. Swarthout

发明人： James A. Kahle ,  Soummya Mallick ,  Robert G. McDonald ,  Edward L. Swarthout

IPC分类号： G06F900

CPC分类号： G06F9/4843 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3851

摘要： A multiscalar processor and method of executing a multiscalar program within a multiscalar processor having a plurality of processing elements and a thread scheduler are provided. The multiscalar program includes a plurality of threads that are each composed of one or more instructions of a selected instruction set architecture. Each of the plurality of threads has a single entry point and a plurality of possible exit points. The multiscalar program further comprises thread code including a plurality of data structures that are each associated with a respective one of the plurality of threads. According to the method, a third data structure among the plurality of data structures is supplied to the thread scheduler. The third data structure, which is associated with a third thread among the plurality of threads, specifies a first data structure associated with a first possible exit point of the third thread and a second data structure associated with a second possible exit point of the third thread. The third thread is assigned to a selected one of the plurality of processing elements for execution. Prior to completing execution of the third thread, the thread scheduler selects from among the first and the second possible exit points of the third thread. In response to the selection, a corresponding one of the first and second data structures is loaded into the thread scheduler for processing.

摘要翻译： 提供了一种在具有多个处理元件和线程调度器的多级数值处理器内执行多级计算机的多级数据处理器和方法。 多节目程序包括多个线程，每个线程由所选择的指令集架构的一个或多个指令组成。 多个线程中的每一个具有单个入口点和多个可能的出口点。 多节目程序还包括线程代码，其包括多个数据结构，每个数据结构与多个线程中的相应一个线程相关联。 根据该方法，将多个数据结构中的第三数据结构提供给线程调度器。 与多个线程中的第三线程相关联的第三数据结构指定与第三线程的第一可能退出点相关联的第一数据结构和与第三线程的第二可能出口点相关联的第二数据结构 。 第三线程被分配给用于执行的多个处理元件中的所选择的一个。 在完成第三线程的执行之前，线程调度器从第三线程的第一和第二可能出口点中选择。 响应于该选择，第一和第二数据结构中相应的一个被加载到线程调度器中进行处理。

公开(公告)号：US5913925A

公开(公告)日：1999-06-22

申请号：US767490

申请日：1996-12-16

申请人： James A. Kahle ,  Soummya Mallick ,  Robert G. McDonald

发明人： James A. Kahle ,  Soummya Mallick ,  Robert G. McDonald

IPC分类号： G06F9/44 ,  G06F9/48 ,  G06F9/38

CPC分类号： G06F9/4843 ,  G06F9/44

摘要： A method and system for constructing a program are provided. According to the method, each of a plurality of instructions are assigned to at least one of a plurality of threads. The plurality of threads include first, second, and third threads, where the third thread follows the first thread and precedes the second thread in a logical program order. A data structure associated with the first thread is then constructed. The data structure includes an indication that execution of the second thread is to be initiated prior to initiation of execution of the third thread. According to one embodiment, the indication within the data structure is a pointer that specifies a second data structure associated with the second thread.

摘要翻译： 提供了一种用于构建程序的方法和系统。 根据该方法，将多个指令中的每一个分配给多个线程中的至少一个。 多个线程包括第一，第二和第三线程，其中第三线程遵循第一线程并且以逻辑程序顺序在第二线程之前。 然后构建与第一线程相关联的数据结构。 数据结构包括在开始执行第三线程之前要启动第二线程的执行的指示。 根据一个实施例，数据结构内的指示是指定与第二线程相关联的第二数据结构的指针。

公开(公告)号：US5887166A

公开(公告)日：1999-03-23

申请号：US767491

申请日：1996-12-16

申请人： Soummya Mallick ,  Robert G. McDonald ,  Edward L. Swarthout

发明人： Soummya Mallick ,  Robert G. McDonald ,  Edward L. Swarthout

IPC分类号： G06F9/48 ,  G06F9/00

CPC分类号： G06F9/4881

摘要： A method and system are provided for constructing a program executable by a processor including one or more processing elements for executing threads and a thread scheduler for assigning threads to the processing elements for execution. According to the method, a plurality of threads are provided that each include at least one control flow instruction. From one or more control flow instructions within the plurality of threads, a condition upon which execution of a particular thread depends is determined. In response to the determination, at least one navigation instruction executable by the thread scheduler is created that indicates that the particular thread is to be assigned to one of the processing elements for execution in response to the condition.

摘要翻译： 提供了一种方法和系统，用于构建可由包括用于执行线程的一个或多个处理元件和用于将线程分配给处理元件以执行的线程调度器的处理器执行的程序。 根据该方法，提供多个线程，每个线程包括至少一个控制流程指令。 从多个线程内的一个或多个控制流程指令，确定特定线程的执行所依赖的状态。 响应于该确定，创建可由线程调度器执行的至少一个导航指令，其指示将特定线程分配给响应于条件执行的一个处理元件。

公开(公告)号：US5805916A

公开(公告)日：1998-09-08

申请号：US758017

申请日：1996-11-27

申请人： Soummya Mallick ,  Michael Putrino ,  Romesh Mangho Jessani

发明人： Soummya Mallick ,  Michael Putrino ,  Romesh Mangho Jessani

IPC分类号： G06F9/302 ,  G06F9/38

CPC分类号： G06F9/30014 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3875

摘要： The present invention relates to a multiple stage execution unit for executing instructions in a microprocessor having a plurality of rename registers for storing execution results, an instruction cache for storing instructions, each instruction being associated with a rename register, a sequencer unit for providing an instruction to the execution unit, and a data cache for providing data to the execution unit. In one version, the execution unit includes a first stage which generates an intermediate result from the data according to an instruction; a means for providing a first portion of the intermediate result to an intermediate register; a means for providing a second portion of the intermediate result to a rename register associated with the instruction; a means for passing the first portion from the intermediate register to a second stage of the execution unit; a means for passing the second portion from the rename register to the second stage of the execution unit; wherein the second stage of the execution unit operates on the first and second portions according to the instruction.

摘要翻译： 本发明涉及一种多级执行单元，用于在微处理器中执行指令，该微处理器具有用于存储执行结果的多个重命名寄存器，用于存储指令的指令高速缓存，每个指令与重命名寄存器相关联，定序器单元用于提供指令 以及用于向执行单元提供数据的数据高速缓存。 在一个版本中，执行单元包括根据指令从数据生成中间结果的第一阶段; 用于将中间结果的第一部分提供给中间寄存器的装置; 用于将中间结果的第二部分提供给与指令相关联的重命名寄存器的装置; 用于将第一部分从中间寄存器传递到执行单元的第二级的装置; 用于将第二部分从重命名寄存器传递到执行单元的第二级的装置; 其中执行单元的第二级根据该指令在第一和第二部分上操作。