Abstract:
There is provided with an interface apparatus. The interface apparatus provides a shared cache for a plurality of processing units. A first port acquires data from a first processing unit included in the plurality of processing units. A second port outputs the data acquired from the first processing unit to a second processing unit included in the plurality of processing units. A cache caches the data acquired from the first processing unit. A controller controls, based on information acquired from the second processing unit, whether to write back data written in the cache to a memory different from the cache.
Abstract:
An image processing apparatus includes: a filter unit configured to execute a filter process on each block area in the input image and output the filter processing result of each pixel in the input image; a supply unit configured to read out attribute information from the attribute map and supply attribute information for each pixel; and an image processing unit configured to perform the predetermined image processing for the filter processing result output by the filter unit based on the attribute information for each pixel supplied by the supply unit, wherein the pixel order in which the pixel value in the input image is received by the filter processing unit and the pixel order in which the filter processing unit outputs the filter processing result are different, and wherein the supply unit supplies the attribute information for each pixel according to the pixel order of the filter processing result.
Abstract:
When processing image data by referring to at least one of reference image data and correction data, an image is processed in a unit of band area by dividing image data of a target image in a plurality of band areas. In this case, the minimum transfer unit of the image data is set. The minimum transfer unit of at least one of the reference image data and the correction data is obtained to process the image data in the minimum transfer unit. The transfer rate of the image data is determined so that the image data to be buffered fits in a capacity of a buffer available in image processing. The height of the band area to be created by division is determined based on the ratio of the transfer rate of the image data to the minimum transfer unit of the image data.
Abstract:
When processing image data by referring to at least one of reference image data and correction data, an image is processed in a unit of band area by dividing image data of a target image in a plurality of band areas. In this case, the minimum transfer unit of the image data is set. The minimum transfer unit of at least one of the reference image data and the correction data is obtained to process the image data in the minimum transfer unit. The transfer rate of the image data is determined so that the image data to be buffered fits in a capacity of a buffer available in image processing. The height of the band area to be created by division is determined based on the ratio of the transfer rate of the image data to the minimum transfer unit of the image data.
Abstract:
In order to allow efficient data communication, an interface device that includes N ports, comprises: a cache memory that is shared by the N ports and includes a plurality of cache tags each of which is allocated to one of the N ports; and N cache determination units corresponding to the N ports. Each of the N cache determination units comprises: a determiner configured to determine, based on all of the values of the plurality of cache tags, whether a cache miss has occurred in the cache memory, and an update unit configured to update, when the determiner determines that a cache miss has occurred, cache tag values allocated to a self-port.
Abstract:
In order to allow efficient data communication, an interface device that includes N ports, comprises: a cache memory that is shared by the N ports and includes a plurality of cache tags each of which is allocated to one of the N ports; and N cache determination units corresponding to the N ports. Each of the N cache determination units comprises: a determiner configured to determine, based on all of the values of the plurality of cache tags, whether a cache miss has occurred in the cache memory, and an update unit configured to update, when the determiner determines that a cache miss has occurred, cache tag values allocated to a self-port.
Abstract:
When processing image data by referring to at least one of reference image data and correction data, an image is processed in a unit of band area by dividing image data of a target image in a plurality of band areas. In this case, the minimum transfer unit of the image data is set. The minimum transfer unit of at least one of the reference image data and the correction data is obtained to process the image data in the minimum transfer unit. The transfer rate of the image data is determined so that the image data to be buffered fits in a capacity of a buffer available in image processing. The height of the band area to be created by division is determined based on the ratio of the transfer rate of the image data to the minimum transfer unit of the image data.
Abstract:
When processing image data by referring to at least one of reference image data and correction data, an image is processed in a unit of band area by dividing image data of a target image in a plurality of band areas. In this case, the minimum transfer unit of the image data is set. The minimum transfer unit of at least one of the reference image data and the correction data is obtained to process the image data in the minimum transfer unit. The transfer rate of the image data is determined so that the image data to be buffered fits in a capacity of a buffer available in image processing. The height of the band area to be created by division is determined based on the ratio of the transfer rate of the image data to the minimum transfer unit of the image data.
Abstract:
In a storage device including a plurality of storage regions, in order to synchronize input/output control of data into/from the storage region, a writing sequence or a reading sequence of the data into or from the storage region is stored, one of the storage regions to be accessed is selected in accordance with the stored sequence, and the synchronization control of input/output processing into/from an intermediate buffer is carried out, which allows an intermediate buffer control mechanism to be applied to various intermediate buffers.
Abstract:
A reading process is performed to read data of each area, which is divided from image data, from a buffer storing the image data to be performed on a predetermined image process. A transmitting process is performed to transmit the read data of the area to an image processor. A reception process is performed to receive data generated in the predetermined image process from the image processor. A parameter for a writing process is set based on an area size of the received data. A writing process is performed to write the received data to the buffer by data transfer using direct memory access (DMA).