公开(公告)号：US20240087550A1

公开(公告)日：2024-03-14

申请号：US18466785

申请日：2023-09-13

Applicant: CASIO COMPUTER CO., LTD.

Inventor： Jun SATO

IPC: G10H1/043

CPC classification number: G10H1/043 ,  G10H2210/325

Abstract: A method for performance data transmission control executed by one or more processors includes receiving performance data associated with output timings, the performance data including continuously varying operation data whose value changes continuously; detecting characteristic points of change from the continuously varying operation data; thinning out the continuously varying operation data other than the characteristic points of the change; and generating unit performance data to be transmitted to an external device, based on the performance data in which the characteristic points in the continuously varying operation data have been detected and in which the continuously varying operation data other than the characteristic points have been thinned out.

公开(公告)号：US20230326437A1

公开(公告)日：2023-10-12

申请号：US18210267

申请日：2023-06-15

Applicant: CASIO COMPUTER CO., LTD.

Inventor： Fuminori SANO ,  Jun SATO ,  Hiroki KANNO

IPC: G10H1/00

CPC classification number: G10H1/0066 ,  G10H1/0083 ,  G10H2240/211 ,  G10H2240/311

Abstract: An electronic equipment according to an embodiment of the present disclosure includes: a reception circuit that receives a musical instrument digital interface (MIDI) message, time stamp information regarding an execution timing of the MIDI message, and offset information regarding buffering of the MIDI message; and a processor that controls the execution timing of the MIDI message according to the time stamp information on a basis of the offset information.

公开(公告)号：US20240105153A1

公开(公告)日：2024-03-28

申请号：US18241445

申请日：2023-09-01

Applicant: CASIO COMPUTER CO., LTD.

Inventor： Jun SATO

IPC: G10H1/00

CPC classification number: G10H1/0066 ,  G10H1/0008 ,  G10H2240/311

Abstract: An electronic device includes at least one processor that outputs an output signal in response to acquisition of information data with which information on output timing is associated with respect to each unit data. The at least one processor is configured to perform control of outputting the output signal in accordance with the unit data, at delayed timing after a lapse of a certain delay setting time period from the output timing, and if output of the output signal is further delayed from the delayed timing, extend the delay setting time period in accordance with a duration of the further delay.