公开(公告)号：US20170221538A1

公开(公告)日：2017-08-03

申请号：US15388419

申请日：2016-12-22

申请人： CHAN KYUNG KIM

发明人： CHAN KYUNG KIM

IPC分类号： G11C11/16

CPC分类号： G11C11/1673 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1675 ,  G11C11/1697

摘要： A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation.

公开(公告)号：US20140146600A1

公开(公告)日：2014-05-29

申请号：US14077274

申请日：2013-11-12

申请人： DONG HYUN SOHN ,  CHAN KYUNG KIM ,  YUN SANG LEE

发明人： DONG HYUN SOHN ,  CHAN KYUNG KIM ,  YUN SANG LEE

IPC分类号： G11C11/16

CPC分类号： G11C11/1697 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

摘要： A magneto-resistive random access memory (MRAM) comprising an MRAM cell array having an MRAM cell, and a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell. The control and voltage generation unit comprising a command decoder configured to generate a decoding signal in response to a command output from a memory controller, and a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and a reset signal output from the memory controller.

摘要翻译： 包括具有MRAM单元的MRAM单元阵列的磁阻随机存取存储器（MRAM）以及被配置为产生MRAM单元的反向偏置电压的控制和电压产生单元。 所述控制和电压产生单元包括命令解码器，其被配置为响应于从存储器控制器输出的命令产生解码信号;以及电压控制器和发生器，被配置为基于所述解码信号产生具有幅度的所述反向偏置电压，以及 从存储器控制器输出的复位信号。