公开(公告)号：US20190051351A1

公开(公告)日：2019-02-14

申请号：US15936696

申请日：2018-03-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： SUK-SOO PYO ,  Hyuntaek Jung ,  Taejoong Song

IPC分类号： G11C13/00 ,  G11C29/50

CPC分类号： G11C13/0028 ,  G11C5/147 ,  G11C7/14 ,  G11C7/227 ,  G11C8/08 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/028 ,  G11C29/50 ,  G11C2013/0054 ,  G11C2029/5006 ,  G11C2213/79 ,  G11C2213/82

摘要： A nonvolatile memory device includes a memory cell including memory cells and dummy cells, a row decoder connected to the memory cells through word lines, a dummy word line bias circuit connected to the dummy cells through dummy word lines, a write driver and sense amplifier connected to the memory cells through bit lines, and a dummy bit line bias circuit connected to the dummy cells through a dummy bit line. The dummy word line bias circuit is configured to apply a same or a different voltage to respective ones of the dummy word lines to turn off selected dummy cells and adjust a leakage current flowing through the dummy cells; and a leakage current in the memory cells is maintained at a substantially uniform level through adjustment of the leakage current in the dummy cells.

公开(公告)号：US20180374525A1

公开(公告)日：2018-12-27

申请号：US16014011

申请日：2018-06-21

申请人： Samsung Electronics Co., Ltd.

发明人： Artur ANTONYAN

IPC分类号： G11C11/16

CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

摘要： A memory device includes a memory cell array that includes memory cells, a row decoder that is connected with the memory cell array through word lines, a column decoder that is connected with the memory cell array through bit lines and source lines, and a write driver that outputs a write voltage in a write operation. The column decoder includes switches, which are respectively connected to the bit lines and are respectively connected to the source lines. During the write operation, a selected switch of the switches transfers the write voltage to a selected bit line of the bit lines. Each unselected switch of the switches electrically separates the write driver from a corresponding unselected bit line of the bit lines by using the write voltage.

公开(公告)号：US20180374502A1

公开(公告)日：2018-12-27

申请号：US15921987

申请日：2018-03-15

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Tazumi NAGASAWA ,  Hirofumi SUTO ,  Michinaga YAMAGISHI ,  Taro KANAO ,  Koichi MIZUSHIMA

IPC分类号： G11B5/39 ,  G11B5/31 ,  G11C11/16 ,  G11C11/56

CPC分类号： G11B5/3909 ,  G11B5/3153 ,  G11C11/161 ,  G11C11/1697 ,  G11C11/5607 ,  H01L43/02 ,  H01L43/08 ,  H03B15/006

摘要： According to one embodiment, an oscillator includes a first element. The first element includes first and second magnetic layers, and a first nonmagnetic layer. The first magnetic layer includes first and second magnetic films, and a first nonmagnetic film. The second magnetic film is provided between the second magnetic layer and the first magnetic film. The first nonmagnetic layer is provided between the second magnetic film and the second magnetic layer. An orientation of a first magnetization of the first magnetic film has a reverse component of an orientation of a second magnetization of the second magnetic film. A first magnetic field is applied to the first element. The first element is in a first state when a first current flows in the first element An electrical resistance of the first element in the first state includes first and second electrical resistances repeating alternately.

公开(公告)号：US20180342278A1

公开(公告)日：2018-11-29

申请号：US16053578

申请日：2018-08-02

申请人： TOSHIBA MEMORY CORPORATION

发明人： Fumiyoshi MATSUOKA

IPC分类号： G11C11/16 ,  G11C13/00 ,  G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/00 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/1697 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054

摘要： A method for controlling a semiconductor storage device includes causing a control circuit to supply first write data to a sub cell area which performs a first operation of supplying a first voltage to a selected sub cell area. The semiconductor storage device includes a cell array including a plurality of memory cells, a sense amplifier reading data of the memory cell, a write driver writing data to the memory cell, the sub cell area including the cell array, the sense amplifier, and the write driver, a memory area including a plurality of sub cell areas, and the control circuit controlling the sense amplifier and the write driver.

公开(公告)号：US10062424B2

公开(公告)日：2018-08-28

申请号：US15652143

申请日：2017-07-17

申请人： SK hynix Inc.

发明人： Yang-Kon Kim ,  Guk-Cheon Kim ,  Jeong-Myeong Kim ,  Jong-Koo Lim ,  Ku-Youl Jung ,  Won-Joon Choi

IPC分类号： G11C11/16 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

CPC分类号： G11C11/1697 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

摘要： This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.

公开(公告)号：US20180158525A1

公开(公告)日：2018-06-07

申请号：US15827626

申请日：2017-11-30

申请人： National Institute of Advanced Science and Technology

发明人： Takayuki Nozaki ,  Yoshishige Suzuki ,  Shinji Yuasa ,  Yoichi Shiota ,  Takurou Ikeura ,  Hiroki Noguchi ,  Kazutaka Ikegami

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C11/1655 ,  G11C11/1675 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/1697 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0064 ,  G11C2013/0076 ,  G11C2013/0092 ,  G11C2213/79

摘要： According to one embodiment, a resistance change type memory includes: a variable resistance element connected between first and second bit lines; a write control circuit including first and second transistors with terminals connected to the first and second bit lines, respectively, and controlling write to the variable resistance element; a first interconnect supplied with a first voltage and connected to the first bit line via the first transistor; and a second interconnect supplied with a second voltage higher than the first voltage, and connected to the first bit line via the second transistor. The write control circuit supplies the second voltage to the first bit line with a first pulse width via the second transistor in the ON state after supplying the first voltage to the first bit line via the first transistor.

公开(公告)号：US20180108412A9

公开(公告)日：2018-04-19

申请号：US15511006

申请日：2015-09-11

申请人： Massachusetts Institute of Technology

发明人： Uwe Bauer ,  Geoffrey S.D. Beach

IPC分类号： G11C13/06

CPC分类号： G11C13/06 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1697 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0069 ,  G11C19/0825 ,  G11C2213/15 ,  G11C2213/53 ,  G11C2213/71 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/146

摘要： Systems, methods, and apparatus are provided for tuning a memristive property of a device. The device (500) includes a layer of a dielectric material (507) disposed over and forming an interface with a layer of an electrically conductive material (506), and a gate electrode (508) disposed over the dielectric material. The dielectric material layer includes at least one ionic species (302) having a high ion mobility. The electrically conductive material is configured such that a potential difference applied to the device can cause the at least one ionic species to migrate reversibly across the interface into or out of the electrically conductive material layer, to modify the resistive state of the electrically conductive material layer.

公开(公告)号：US09928903B2

公开(公告)日：2018-03-27

申请号：US15248216

申请日：2016-08-26

申请人： TOSHIBA MEMORY CORPORATION

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G11C13/00 ,  G11C7/04 ,  G11C11/16

CPC分类号： G11C13/0004 ,  G11C7/04 ,  G11C11/1655 ,  G11C11/1675 ,  G11C11/1697 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/72

摘要： According to one embodiment, a semiconductor storage device includes: a memory cell including a variable resistance element; a bit line coupled to the memory cell; and a first circuit applying a first voltage to the bit line in a write operation for the memory cell. When a temperature of the variable resistance element is lower than or equal to a first temperature, a temperature coefficient of the first voltage is 0. When the temperature of the variable resistance element is higher than the first temperature, the temperature coefficient of the first voltage is negative.

公开(公告)号：US20180033476A1

公开(公告)日：2018-02-01

申请号：US15553051

申请日：2016-01-14

申请人： SONY CORPORATION

发明人： MIKIO OKA ,  YASUO KANDA ,  YUTAKA HIGO

IPC分类号： G11C11/16

CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1697 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2213/15 ,  G11C2213/74 ,  G11C2213/79 ,  H01L43/08

摘要： An object of the present technology is to improve the performance of a memory cell that stores the value reflecting the direction of an electric current. The memory cell includes an N-type transistor, a P-type transistor, and a storage element. The N-type transistor supplies a current either from a source to a drain thereof or from the drain to the source. The P-type transistor supplies a current from a source to a drain thereof. The storage element stores a logical value reflecting the direction of the current supplied from the drain of the N-type transistor and from the drain of the P-type transistor.

公开(公告)号：US09779024B2

公开(公告)日：2017-10-03

申请号：US15051132

申请日：2016-02-23

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kazutaka Ikegami ,  Hiroki Noguchi

IPC分类号： G11C8/00 ,  G06F12/0875 ,  G11C11/16 ,  G06F12/02 ,  G06F1/26 ,  G06F12/0868

CPC分类号： G06F12/0875 ,  G06F1/26 ,  G06F12/0238 ,  G06F12/0868 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/452 ,  G11C11/1675 ,  G11C11/1677 ,  G11C11/1697 ,  Y02D10/13

摘要： A semiconductor storage device has a non-volatile memory, a memory controller to carry out write processing to the non-volatile memory using a write pulse, and a write pulse controller to select one of a first write mode for writing to the non-volatile memory and a second write mode for writing to the non-volatile memory with higher electric power consumption than the first write mode at higher speed than the first write mode and, when the first write mode is selected, set a pulse width of the write pulse such that the pulse width is shorter than one cycle of a clock signal used to control access to the non-volatile memory,