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公开(公告)号：US11894101B2
公开(公告)日：2024-02-06
申请号：US17647552
申请日：2022-01-10
发明人： Hsin-Cheng Su
CPC分类号： G11C7/12 , G11C7/08 , G11C7/1096
摘要： Sense amplifier, memory and control method are provided. The sense amplifier includes: amplify module configured to amplify voltage difference between bit line and reference bit line when the sense amplifier is in amplifying stage; write module connected to the bit line and the reference bit line, and configured to pull the voltage difference between the bit line and the reference bit line according to data to be written when the sense amplifier is in write stage; controllable power module connected to the amplify module, configured to provide first voltage to the amplify module when the sense amplifier is in non-write stage, and to provide second voltage to the amplify module when the sense amplifier in write stage. Herein, the second voltage is less than the first voltage, and the second voltage is in positive correlation with the drive capability of the write module.
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公开(公告)号：US12112825B2
公开(公告)日：2024-10-08
申请号：US17655323
申请日：2021-07-21
发明人： Hsin-Cheng Su
IPC分类号： G11C11/4091 , G11C7/08
CPC分类号： G11C7/08 , G11C11/4091
摘要： The present application provides a sense amplifier, a memory, and a control method. The sense amplifier includes: an amplification module, configured to amplify a voltage difference between a bit line and a reference bit line when the sense amplifier is at an amplification stage; and a controlled power module, connected to the amplification module, and configured to: determine a drive parameter according to a rated compensation voltage range between the bit line and the reference bit line, and supply power to the amplification module according to the drive parameter, so as to control the amplification module to pull a compensation voltage between the bit line and the reference bit line to be a rated compensation voltage at an offset cancellation stage, where the rated compensation voltage is within the rated compensation voltage range.
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公开(公告)号：US12094562B2
公开(公告)日：2024-09-17
申请号：US17647995
申请日：2022-01-14
发明人： Hsin-Cheng Su
摘要： The present application provides a sense amplifier, a memory, and a control method. The sense amplifier includes: an amplification module, configured to: amplify a voltage difference between a bit line and a reference bit line; and a controlled power supply module, connected to the amplification module, and configured to: determine a drive parameter according to a first rated pull rate range and a second rated pull rate range, and supply power to the amplification module according to the drive parameter, to control the amplification module to pull a voltage of the bit line or a voltage of the reference bit line to a first preset value at a first rated pull rate at the amplification stage and pull the voltage of the reference bit line or the voltage of the bit line to a second preset value at a second rated pull rate at the amplification stage.
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公开(公告)号：US12033690B2
公开(公告)日：2024-07-09
申请号：US17842161
申请日：2022-06-16
发明人： Hsin-Cheng Su
IPC分类号： G11C7/12 , G11C11/4074 , G11C11/4091 , G11C11/4094 , G11C11/4096
CPC分类号： G11C11/4091 , G11C11/4074 , G11C11/4094 , G11C11/4096
摘要： A sense amplifier (SA), a memory and a control method are provided. The SA includes an amplifying module, configured to amplify voltage difference between a BL and a BLB when the SA is in an amplifying stage; a controllable power module, connected to the amplifying module and configured to stop providing power to the amplifying module when the SA is in a writing stage, to enable the amplifying module to stop working; and a writing module, connected to the BL and the BLB and configured to pull the voltage difference between the BL and the BLB according to data to be written when the SA is in the writing stage. The solution may ensure the successful data writing in a storage unit in a case that a writing circuit has weak drive capability.
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公开(公告)号：US11823763B2
公开(公告)日：2023-11-21
申请号：US17449658
申请日：2021-09-30
发明人： Hsin-Cheng Su
CPC分类号： G11C7/08 , G11C7/062 , G11C7/1096 , G11C7/12
摘要： A sense amplifier includes: an amplification module, configured to amplify a voltage difference between a bit line and a reference bit line when the sense amplifier is in an amplification phase; a controllable power module, connected to the amplification module and configured to supply a first voltage to the amplification module when the sense amplifier is in a writing phase, and supply a second voltage to the amplification module when the sense amplifier is in a non-writing phase, and the second voltage is greater than the first voltage; and a writing module, connected to the bit line and the reference bit line and configured to pull the voltage difference between the bit line and the reference bit line according to to-be-written data when the sense amplifier is in the writing phase.
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6.发明公开公开(公告)号：US20230395119A1
公开(公告)日：2023-12-07
申请号：US18454104
申请日：2023-08-23
发明人： Xian FAN , Yinchuan Gu , Xianlei Cao , Yu Yang , Hsin-Cheng Su
IPC分类号： G11C11/406 , G11C11/4072
CPC分类号： G11C11/40615 , G11C11/4072 , G11C11/40618
摘要： A refresh address counting circuit, a refresh address counting method, and a refresh address read-write circuit are provided. The refresh address counting circuit includes: a self-oscillation clock generation circuit, configured to generate, in each of refresh cycles, a self-oscillation clock signal based on at least one array activation signal upon acquiring a refresh signal; a self-oscillation mask circuit, configured to generate a self-oscillation mask signal under a preset refresh command; and a refresh address counter, configured to counting a refresh address based on the self-oscillation clock signal and the self-oscillation mask signal and to output a self-oscillation refresh address.
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