公开(公告)号：US20210376059A1

公开(公告)日：2021-12-02

申请号：US17401472

申请日：2021-08-13

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Jun XIA ,  Tao Liu ,  Qiang Wan ,  Jungsu Kang ,  Kangshu Zhan ,  Sen Li

IPC: H01L49/02

Abstract: The method for preparing the hole in the semiconductor device includes: providing a base to be etched and forming a mask layer on the base to be etched; forming a first pattern layer arranged in an array on the mask layer; etching the mask layer by using the first pattern layer as a mask to form a first hole and a second pattern layer; depositing a protective layer on a side of the second pattern layer away from the base to be etched, the protective layer simultaneously covering a side wall and a bottom portion of the first hole; etching the protective layer which covers the bottom portion of the first hole; and etching a supporting layer by using the second pattern layer and the protective layer which covers the side wall of the first hole as a mask to form a second hole.

公开(公告)号：US12198932B2

公开(公告)日：2025-01-14

申请号：US17457970

申请日：2021-12-07

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Jungsu Kang ,  Sen Li ,  Qiang Wan ,  Tao Liu

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/308

Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate, and forming a first sacrificial layer on the substrate, where the first sacrificial layer includes a first sacrificial dielectric layer and a second sacrificial dielectric layer; patterning the first sacrificial layer, and forming first intermediate pattern structures that are arranged at intervals, where a first gap is provided between two adjacent first intermediate pattern structures; forming a first spacer pad layer in the first gap, where the first spacer pad layer covers sidewalls of each of the two adjacent first intermediate pattern structures and a bottom of the first gap; removing the first spacer pad layer at the bottom of the first gap, and the second sacrificial dielectric layer; and removing the first sacrificial dielectric layer, to form first pattern structures.

公开(公告)号：US11348820B2

公开(公告)日：2022-05-31

申请号：US17648205

申请日：2022-01-18

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Jiangyi Jin ,  Jungsu Kang

IPC: H01T23/00 ,  H01L21/683 ,  H01L21/67

Abstract: The present disclosure relates to an installation fixture for an electrode plate of a semiconductor equipment. The installation fixture includes: an alignment assembly, including a support disc and at least two guide shafts, where the support disc is provided with at least two positioning holes, at least two fixing holes and at least two mounting holes; a drive assembly, including a mounting plate assembly, at least two support rods and a drive rod assembly, where the support rods are connected to the mounting plate assembly, and one end of each of the support rods is connected to one of the mounting holes; and the drive rod assembly is connected to the mounting plate assembly; and a support assembly, including at least two support bases, where each of the support bases is provided with a mounting groove.