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公开(公告)号：US20250038944A1
公开(公告)日：2025-01-30
申请号：US18227799
申请日：2023-07-28
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： YU LIAO , JUNQING SUN
IPC: H04L7/00
Abstract: Fast sampling phase and frequency acquisition suitable for incorporation into various high bandwidth receivers and receiving methods. One illustrative integrated circuit receiver or “deserializer” design has: a clock circuit that provides a sample clock; an analog to digital converter that samples a receive signal in accordance with the sample clock to provide receive signal samples; and a clock recovery circuit. The clock recovery circuit includes: a phase and frequency acquisition module to determine and correct an initial frequency offset and an initial phase offset of the sample clock; and a feedback circuit to minimize timing error of the sample clock after the initial frequency offset and initial phase offset have been corrected.
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公开(公告)号：US20240388312A1
公开(公告)日：2024-11-21
申请号：US18198636
申请日：2023-05-17
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： CHANG SHU , YU LIAO , JUNQING SUN
Abstract: An illustrative decoder includes: a syndrome calculator, a location finder, and an error corrector. The syndrome calculator has an array of logic gates to obtain syndrome values as a product of a receive message vector and a parity check matrix, the syndrome values including at least a three ten-bit syndrome values S1, S2, and S3. The location finder derives a number of errors from the syndrome values, and uses a second array of logic gates to obtain two polynomial roots as a product of a syndrome value vector and a quadratic solution matrix when the number of errors is two, the quadratic solution matrix corresponding to a determination of a quadratic equation's trailing coefficient value s, a determination of the quadratic equation's roots, and a reversal of a variable substitution. The location finder further determines a bit index for each of the polynomial roots.
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公开(公告)号：US11300613B2
公开(公告)日：2022-04-12
申请号：US17022311
申请日：2020-09-16
Applicant: Credo Technology Group Limited
Inventor： Arshan Aga , Haoli Qian , Junqing Sun , James Bartenslager
IPC: G01R31/317 , G01R29/26
Abstract: A method of assessing the ability of one or more multi-die circuit elements to tolerate the presence of jitter in intra-package. The method includes: providing a first die having a set of transmitters for digital communications, the set of transmitters comprising a first transmitter and a second transmitter; providing a second die having a set of receivers for digital communications; providing a performance monitor; coupling, using an intra-package trace, a first transmit signal from the first transmitter to a receiver of the set of receivers; coupling a second transmit signal from the second transmitter to an external pin; supplying an input signal that induces jitter in the first and second transmit signals; measuring jitter in the second transmit signal via the external pin; and determining, using the performance monitor, a performance characteristic of the second die.
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公开(公告)号：US20220021603A1
公开(公告)日：2022-01-20
申请号：US16932988
申请日：2020-07-20
Applicant: Credo Technology Group Limited
Inventor： Haoli Qian , Calvin Xiong Fang , William Brennan , Jeffrey Twombly
IPC: H04L12/707 , H04L12/26
Abstract: Active Ethernet cables that provide data path redundancy. One illustrative cable embodiment includes a first connector connected to each of a second and third connectors, the first connector including a multiplexer that couples a data stream from a selectable one of the second and third connectors to an output of the first connector. One illustrative method embodiment includes: producing from an output of a first connector a data stream from a currently selected one of multiple redundant connectors; monitoring the data stream for a fault associated with the currently selected one of multiple redundant connectors; and responsive to detecting said fault, producing from the output of the first connector a data stream from a different selected one of the multiple redundant connectors.
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公开(公告)号：US11196592B1
公开(公告)日：2021-12-07
申请号：US16937773
申请日：2020-07-24
Applicant: Credo Technology Group Limited
Inventor： Fang Cai , Junqing (Phil) Sun , Haoli Qian
Abstract: Equalization methods and equalizers employing discrete-time filters are provided with dynamic perturbation effect based adaptation. Tap coefficient values may be individually perturbed during the equalization process and the effects on residual ISI monitored to estimate gradient components or rows of a difference matrix. The gradient or difference matrix components may be assembled and filtered to obtain components suitable for calculating tap coefficient updates with reduced adaptation noise. The dynamic perturbation effect based updates may be interpolated with precalculated perturbation effect based updates to enable faster convergence with better accommodation of analog component performance changes attributable to variations in process, supply voltage, and temperature.
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Patent Agency Ranking
公开(公告)号：US20210375798A1
公开(公告)日：2021-12-02
申请号：US17194390
申请日：2021-03-08
Applicant: Credo Technology Group Limited
Inventor： Mengying MA , Xike LIU , Xiangxiang YE , Xin WANG
IPC: H01L23/66 , H03H11/28 , H03M9/00 , H01L23/00 , H01L23/498
Abstract: An illustrative embodiment of a packaged integrated circuit includes: an integrated circuit chip having a SerDes signal pad; and a package substrate having a core via and an arrangement of micro-vias connecting the SerDes signal pad to an external contact for solder ball connection to a PCB trace. The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance, and the arrangement of micro-vias provides a pi-network inductance that improves connection impedance matching. An illustrative method embodiment includes: obtaining an expected impedance of the PCB trace; determining parasitic capacitances of a core via and a solder ball connection to the PCB trace; minimizing the core via capacitance; calculating a pi-network inductance that improves impedance matching with the PCB trace; and adjusting a micro-via arrangement between the core via and the solder ball connection to provide the pi-network inductance.
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公开(公告)号：US11032111B2
公开(公告)日：2021-06-08
申请号：US16552927
申请日：2019-08-27
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Junqing Sun , Haoli Qian
Abstract: An illustrative SerDes (serializer-deserializer) communications method embodiment may include a transceiver: selecting one of multiple registers to specify initial pre-equalizer coefficient values; updating the initial pre-equalizer coefficient values during a training phase; and using the updated pre-equalizer coefficient values to convey a transmit data stream. In an illustrative embodiment of a chip-to-module communications link, a port connector couples a port transceiver to a pluggable module transceiver, the pluggable module transceiver including: one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.
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公开(公告)号：US10992501B1
公开(公告)日：2021-04-27
申请号：US16836553
申请日：2020-03-31
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Junqing Sun , Haoli Qian
Abstract: An illustrative integrated receiver circuit embodiment includes: a set of analog-to-digital converters that sample a receive signal in response to staggered clock signals to provide a parallel set of sampled receive signals; an equalizer that converts the parallel set of sampled receive signals into a parallel set of equalized signals; one or more quantizers that derives symbol decisions from the parallel set of equalized signals; a digital timing circuit that generates the staggered clock signals based on the parallel set of equalized signals; and a clock skew adjustment circuit that provides a controllable skew of at least one of said staggered clock signals relative to at least one other of the staggered clock signals. A monitor circuit is included to provide a reliability indicator for the symbol decisions, as is a controller that determines a dependence of the reliability indicator on the controllable skew.
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公开(公告)号：US10818608B2
公开(公告)日：2020-10-27
申请号：US15781782
申请日：2017-04-10
Applicant: Credo Technology Group Limited
IPC: H01L23/552 , H01L23/00 , H01L23/538 , H01L23/498 , H01L23/64 , H03B5/12 , H01F17/00 , H04L7/00
Abstract: Disclosed microelectronic assemblies employ an integrated interposer cage to reduce electromagnetic interference with (and from) high-frequency components. One illustrative embodiment includes: at least one IC die having drive cores for a plurality of oscillators, the IC die attached in a flip-chip configuration to a (interposer) substrate, the substrate having: multiple inductors electrically coupled to said drive cores and each enclosed within a corresponding conductive cage integrated into the substrate to reduce mutual coupling between the inductors and noise coupled through substrate. An illustrative interposer embodiment includes: upper contacts arranged to electrically connect with micro bumps on at least one IC die; metallization and dielectric layers that form multiple inductors each surrounded by bars of a conductive cage; lower contacts arranged to electrically connect with bumps on a package substrate; and a substrate with a plurality of TSVs (through-silicon vias) that electrically couple to the lower contacts. Each of the bars includes: at least one of said TSVs, at least one via through the metallization and dielectric layers, and at least one upper contact.
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公开(公告)号：US20200220550A1
公开(公告)日：2020-07-09
申请号：US16240702
申请日：2019-01-04
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Arshan Aga , Xiang Gao , Ni Xu
Abstract: An illustrative PLL circuit and method for generating a clock signal over a wide frequency range without gaps. In one illustrative embodiment, an extended-range PLL includes: a phase comparator that determines a phase error between a reference clock and a feedback clock; a loop filter that converts the phase error into a control signal; a voltage controlled oscillator (VCO) that provides a generated clock signal having a generated clock frequency determined by the control signal; a divide-by-1.5 block that produces a reduced-frequency clock signal in response to the generated clock signal; and a multiplexer that selects one of the generated clock signal and the reduced-frequency clock signal as a selected clock signal.
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