Fractional-N PLL based clock recovery for SerDes

    公开(公告)号:US10313105B2

    公开(公告)日:2019-06-04

    申请号:US15702715

    申请日:2017-09-12

    Abstract: An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop, a phase interpolator, a sampling element, a phase detector, a phase control filter, and a frequency control filter. The phase interpolator applies a controllable phase shift to the clock signal from the frac-N PLL to provide a sampling signal to the sampling element. The phase detector estimates timing error of the sampling signal relative to the analog receive signal. The phase control filter derives a phase control signal for the phase interpolator which operates to minimize a phase component of the estimated timing error. The frequency control filter derives the frequency control signal in a fashion that separately minimizes a frequency offset component of the estimated timing error, reducing the interpolator's phase rotation rate.

    Onboard/co-packaged optics with transmit-side equalization

    公开(公告)号:US11616576B2

    公开(公告)日:2023-03-28

    申请号:US17305434

    申请日:2021-07-07

    Abstract: Transmit-side equalization is disclosed for network devices and network communications methods employing onboard/co-packaged optics. An illustrative network device includes a substrate having a host device IC (integrated circuit) and an optical module IC connected by a short-reach link. The optical module IC having a transmit chain includes a CTLE (continuous time linear equalizer) to at least partly compensate for a channel response of the short-reach link, and a driver that amplifies an output of the CTLE for a photoemitter that couples to an optical fiber. The host device IC includes: a parallel-to-serial converter that produces a digital symbol stream; a digital to analog converter that supplies an analog signal to the short-reach link; and a pre-equalizer coupling the parallel-to-serial converter to the digital-to-analog converter, the pre-equalizer filtering the digital symbol stream to at least partly compensate for a channel response of a combined channel that includes the short-reach link, the CTLE, the driver, and the photoemitter.

    Active redundant Y-cable with power sharing

    公开(公告)号:US11942730B2

    公开(公告)日:2024-03-26

    申请号:US17305798

    申请日:2021-07-14

    Abstract: Active cables and communication methods can provide data path redundancy with power sharing. In one illustrative cable implementation, the cable includes a first connector with contacts to supply power to circuitry in the first connector; a second connector with contacts to supply power to a component of the circuitry in the first connector via a first connection that prevents reverse current flow; and a third connector with contacts to supply power to the same component via a second connection that prevents reverse current flow. An illustrative method implementation includes: using contacts of a first connector to supply power to circuitry in the first connector; and using contacts in each of multiple redundant connectors to supply power to a component of said circuitry in the first connector via a corresponding diodic or switched connection that prevents reverse current flow.

    ACTIVE REDUNDANT Y-CABLE WITH POWER SHARING

    公开(公告)号:US20220385000A1

    公开(公告)日:2022-12-01

    申请号:US17305798

    申请日:2021-07-14

    Abstract: Active cables and communication methods can provide data path redundancy with power sharing. In one illustrative cable implementation, the cable includes a first connector with contacts to supply power to circuitry in the first connector; a second connector with contacts to supply power to a component of the circuitry in the first connector via a first connection that prevents reverse current flow; and a third connector with contacts to supply power to the same component via a second connection that prevents reverse current flow. An illustrative method implementation includes: using contacts of a first connector to supply power to circuitry in the first connector; and using contacts in each of multiple redundant connectors to supply power to a component of said circuitry in the first connector via a corresponding diodic or switched connection that prevents reverse current flow.

    Active cable with remote end control access

    公开(公告)号:US12105659B2

    公开(公告)日:2024-10-01

    申请号:US17805158

    申请日:2022-06-02

    CPC classification number: G06F13/4068 G06F8/61

    Abstract: Cable designs and methods are provided herein to enable remote end access to active cable controllers for monitoring and upgrade operations. One illustrative network cable design includes: a first end connector configured to couple with a first host port and a second end connector configured to couple with a second host port, each of the first and second end connectors configured to convey a data stream in each direction via optical or electrical conductors connected between the first and second end connectors; a controller and a powered transceiver circuit included in the first end connector, the controller operable to configure operation of the powered transceiver circuit; and electrical contacts in the second end connector for a management bus to convey information from the second host port to the controller in the first end connector.

    ACTIVE CABLE WITH REMOTE END CONTROL ACCESS
    6.
    发明公开

    公开(公告)号:US20230394003A1

    公开(公告)日:2023-12-07

    申请号:US17805158

    申请日:2022-06-02

    CPC classification number: G06F13/4068 G06F8/61

    Abstract: Cable designs and methods are provided herein to enable remote end access to active cable controllers for monitoring and upgrade operations. One illustrative network cable design includes: a first end connector configured to couple with a first host port and a second end connector configured to couple with a second host port, each of the first and second end connectors configured to convey a data stream in each direction via optical or electrical conductors connected between the first and second end connectors; a controller and a powered transceiver circuit included in the first end connector, the controller operable to configure operation of the powered transceiver circuit; and electrical contacts in the second end connector for a management bus to convey information from the second host port to the controller in the first end connector.

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