公开(公告)号：US20170358657A1

公开(公告)日：2017-12-14

申请号：US15541155

申请日：2015-09-28

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Feng HUANG ,  Guangtao HAN ,  Guipeng SUN ,  Feng LIN ,  Longjie ZHAO ,  Huatang LIN ,  Bing ZHAO ,  Lixiang LIU ,  Liangliang PING ,  Fengying CHEN

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L21/311 ,  H01L29/739 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265

CPC分类号： H01L29/66325 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/26513 ,  H01L21/31116 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7393 ,  H01L29/78

摘要： The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching and injecting N-type ions between the mini oxide layer (60) and the STI (40) adjacent to the mini oxide layer (60) to form a drain electrode, and at the same time forming a source electrode (51) inside the second P well (34).

公开(公告)号：US20170133505A1

公开(公告)日：2017-05-11

申请号：US15318857

申请日：2015-06-30

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Guangtao HAN ,  Guipeng SUN

IPC分类号： H01L29/78 ,  H01L29/47 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

CPC分类号： H01L29/7831 ,  H01L29/0607 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/408 ,  H01L29/4238 ,  H01L29/47 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66681 ,  H01L29/66901 ,  H01L29/782 ,  H01L29/808

摘要： The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the substrate, a first well region (32) and a second well region (34) that are on the buried layer, a source lead-out region (50), a drain lead-out region (60), and a first gate lead-out region (42) that are in the first well region (32), and a second gate lead-out region (44) in the second well region (34). A Schottky junction interface (70) is disposed on the surface of the first well region (32). The Schottky junction interface (70) is located between the first gate lead-out region (42) and the drain lead-out region (60), and is isolated from the first gate lead-out region (42) and the drain lead-out region (60) by means of isolation structures. The present invention also relates to a manufacturing method for a junction field effect transistor.