公开(公告)号：US20240363338A1

公开(公告)日：2024-10-31

申请号：US18766582

申请日：2024-07-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Chang Liu

IPC: H01L21/02 ,  H01L23/532 ,  H01L29/51

CPC classification number: H01L21/02211 ,  H01L21/02126 ,  H01L23/53295 ,  H01L29/517

Abstract: A method of forming a semiconductor device includes the following operations. A substrate is provided with a device and an insulating layer disposed over the device. A silicon-containing heterocyclic compound precursor and a first oxygen-containing compound precursor are introduced to the substrate, so as to form a zeroth dielectric layer on the insulating layer. A zeroth metal layer is formed in the zeroth dielectric layer. A silicon-containing linear compound precursor and a second oxygen-containing compound precursor are introduced to the substrate to form a first dielectric layer on the zeroth dielectric layer. A first metal layer is formed in the first dielectric layer.

公开(公告)号：US12112984B2

公开(公告)日：2024-10-08

申请号：US17192600

申请日：2021-03-04

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Tsui-Ling Yen ,  Chien-Hung Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/417 ,  H01L21/02

CPC classification number: H01L21/76897 ,  H01L21/76831 ,  H01L21/76844 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41725 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271

Abstract: A semiconductor device includes a conductive feature, a dielectric layer disposed over the conductive feature, and a contact feature extending through the dielectric layer. The contact feature has an upper portion and a lower portion. The upper portion is spaced apart from the dielectric layer with a spacer layer. The lower portion is electrically coupled to the conductive feature and in contact with the dielectric layer.

公开(公告)号：US20240321589A1

公开(公告)日：2024-09-26

申请号：US18680496

申请日：2024-05-31

Applicant: Applied Materials, Inc.

Inventor： Zeqing SHEN ,  Bo QI ,  Abhijit B. MALLICK

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31144 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/31111

Abstract: Embodiments of the present disclosure generally relate to fabricating electronic devices, such as memory devices. In one or more embodiments, a microelectronic device is provided and includes a film stack disposed on a substrate and a patterned hard mask disposed on an upper surface of the film stack. The film stack has a stack thickness and contains a plurality of alternating layers of oxide layers and nitride layers. The microelectronic device also includes a plurality of openings having a depth disposed between a plurality of structures, each structure has a sidewall and each opening has a bottom, the depth is less than the stack thickness, and each opening has an aspect ratio of greater than 50 relative to the depth. The microelectronic device also includes an etch protection liner disposed on the patterned hard mask and the sidewalls.

公开(公告)号：US12087572B2

公开(公告)日：2024-09-10

申请号：US17598830

申请日：2020-03-26

Applicant: Lam Research Corporation

Inventor： Bart J. van Schravendijk ,  Soumana Hamma ,  Kai-Lin Ou ,  Ming Li ,  Malay Milan Samantaray

IPC: H01L21/02 ,  H01L21/311 ,  H01L27/088 ,  H01L27/1157 ,  H10B43/20 ,  H10B43/35

CPC classification number: H01L21/0217 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31111 ,  H01L27/088 ,  H10B43/20 ,  H10B43/35

Abstract: Disclosed are methods for the formation of silicon nitride (SiN) on only the horizontal surfaces of structures such as 3D NAND staircase. This allows for thicker landing pads for subsequently formed vias. In some embodiments, the methods involve deposition of a SiN layer over a staircase followed by a treatment to selectively densify the SiN layer on the horizontal surfaces with respect to the sidewall surfaces. A wet etch is then performed to remove SiN from the sidewall surfaces. The selective treatment results in significantly different wet etch rates (WERs) between the horizontal surfaces and the sidewalls.

公开(公告)号：US12087561B2

公开(公告)日：2024-09-10

申请号：US18329791

申请日：2023-06-06

Applicant: Lam Research Corporation

Inventor： John Stephen Drewery ,  Tom A. Kamp ,  Haoquan Yan ,  John Edward Daugherty ,  Ali Sucipto Tan ,  Ming-Kuei Tseng ,  Bruce Edmund Freeman

IPC: H01J37/32 ,  C23C16/02 ,  C23C16/44 ,  C23C16/455 ,  H01L21/02 ,  H01L21/311 ,  H01L21/67 ,  H01L21/683

CPC classification number: H01J37/32862 ,  C23C16/0236 ,  C23C16/4405 ,  C23C16/45544 ,  H01J37/32449 ,  H01J37/32834 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/67069 ,  H01J37/3211 ,  H01J37/32715 ,  H01J2237/1825 ,  H01J2237/186 ,  H01J2237/3321 ,  H01J2237/3341 ,  H01L21/02164 ,  H01L21/6833

Abstract: A processing chamber such as a plasma etch chamber can perform deposition and etch operations, where byproducts of the deposition and etch operations can build up in a vacuum pump system fluidly coupled to the processing chamber. A vacuum pump system may have multiple roughing pumps so that etch gases can be diverted a roughing pump and deposition precursors can be diverted to another roughing pump. A divert line may route unused deposition precursors through a separate roughing pump. Deposition byproducts can be prevented from forming by incorporating one or more gas ejectors or venturi pumps at an outlet of a primary pump in a vacuum pump system. Cleaning operations, such as waferless automated cleaning operations, using certain clean chemistries may remove deposition byproducts before or after etch operations.

公开(公告)号：US20240290612A1

公开(公告)日：2024-08-29

申请号：US18409549

申请日：2024-01-10

Applicant: Applied Materials, Inc.

Inventor： Zeqing SHEN ,  Supriya GHOSH ,  Susmit Singha ROY ,  Abhijit Basu MALLICK ,  Nitin K. INGLE

IPC: H01L21/02 ,  C23C16/04 ,  C23C16/24 ,  C23C16/56

CPC classification number: H01L21/0217 ,  C23C16/04 ,  C23C16/24 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02247 ,  H01L21/02271

Abstract: The present disclosure generally relates to methods for forming silicon nitride film layers on substrates. In an embodiment, the method includes positioning a substrate having at least one feature thereon in a process chamber, depositing a first silicon film layer on a non-silicon oxide surface of the substrate for a time duration of about 1 to about minutes, nitriding the first silicon film layer to form a first silicon nitride film layer on the substrate, selectively depositing a second silicon film layer on the first silicon nitride film layer, and nitriding the second silicon film layer to form a second silicon nitride film layer disposed directly on the first silicon nitride film layer.

公开(公告)号：US12074058B2

公开(公告)日：2024-08-27

申请号：US18308937

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Shing-Chyang Pan ,  Ching-Yu Chang ,  Wan-Lin Tsai ,  Jung-Hau Shiu ,  Tze-Liang Lee

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76879

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.

公开(公告)号：US20240274433A1

公开(公告)日：2024-08-15

申请号：US18456642

申请日：2023-08-28

Applicant: Tokyo Electron Limited

Inventor： Tsuyoshi TSUNATORI ,  Takayuki KOMIYA

IPC: H01L21/02 ,  C23C16/04 ,  C23C16/34 ,  C23C16/455 ,  C23C16/50 ,  H01J37/32

CPC classification number: H01L21/0228 ,  C23C16/045 ,  C23C16/345 ,  C23C16/45542 ,  C23C16/50 ,  H01J37/32449 ,  H01L21/0217 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/02274 ,  H01J2237/332

Abstract: A substrate processing method of embedding a silicon nitride film in a recess formed in a surface of a substrate, includes repeating a cycle, the cycle including: a first operation of supplying a silicon precursor to form an adsorption layer of the silicon precursor on the substrate; a second operation of supplying a first nitrogen-containing gas and supplying a first power to an upper electrode to generate a first plasma, and exposing the substrate to the first plasma to nitride the adsorption layer and form the silicon nitride film; and a third operation of supplying a second nitrogen-containing gas and supplying a second power to a lower electrode to generate a second plasma different from the first plasma, and exposing the substrate to the second plasma to modify an upper portion of the recess and form an adsorption-inhibiting area.

公开(公告)号：US12062538B2

公开(公告)日：2024-08-13

申请号：US17594744

申请日：2020-04-14

Applicant: Lam Research Corporation

Inventor： Jengyi Yu ,  Samantha S. H. Tan ,  Liu Yang ,  Chen-Wei Liang ,  Boris Volosskiy ,  Richard Wise ,  Yang Pan ,  Da Li ,  Ge Yuan ,  Andrew Liang

IPC: H01L21/02

CPC classification number: H01L21/0228 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274

Abstract: Provided herein are methods and systems for reducing roughness of an EUV resist and improving etched features. The methods involve descumming an EUV resist, filling divots of the EUV resist, and protecting EUV resists with a cap. The resulting EUV resist has smoother features and increased selectivity to an underlying layer, which improves the quality of etched features. Following etching of the underlying layer, the cap may be removed.

公开(公告)号：US20240249947A1

公开(公告)日：2024-07-25

申请号：US18434553

申请日：2024-02-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Yun PENG ,  Chung-Chi KO ,  Keng-Chu LIN

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/28158 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/76224

Abstract: A device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first conductor is in the first dielectric layer. The etch stop layer is over the first dielectric layer. The etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. The second dielectric layer is over the etch stop layer. The second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor.