公开(公告)号：US09520400B2

公开(公告)日：2016-12-13

申请号：US14398849

申请日：2013-05-19

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Shizhen Sun ,  Hao Fang ,  Yong Gu

IPC分类号： H01L27/105 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115 ,  H01L21/283 ,  H01L29/423

CPC分类号： H01L27/1052 ,  H01L21/28273 ,  H01L21/283 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： A NOR flash memory and its manufacturing method are provided in the present disclosure, they are in the field of flash memory. In the manufacturing method, a mask dielectric layer is formed on a second polysilicon layer of a gate stack structure. In addition, part of the mask dielectric layer is etched patternedly to expose part of the second polysilicon layer which is close to a source. Furthermore, the exposed second polysilicon layer is self aligned to form a metal silicide layer. Thus in the NOR flash memory, an unetched mask dielectric layer is substantially located between a metal silicide layer and a drain contacting hole of the NOR flash memory. A drain current between the gate electrode and the drain electrode is small, the above manufacturing method is not complex, a process window is large, a side effect is small, which are advantageous to large scale production.

摘要翻译： 在本公开中提供了NOR闪存及其制造方法，它们在闪存的领域中。 在制造方法中，在栅极堆叠结构的第二多晶硅层上形成掩模电介质层。 此外，掩模介电层的一部分被图案化地蚀刻以暴露靠近源极的第二多晶硅层的部分。 此外，暴露的第二多晶硅层自对准以形成金属硅化物层。 因此，在NOR闪速存储器中，未蚀刻的掩模介电层基本上位于NOR闪存的金属硅化物层和漏极接触孔之间。 栅电极和漏电极之间的漏极电流小，上述制造方法不复杂，工艺窗口大，副作用小，有利于大规模生产。

公开(公告)号：US20150118838A1

公开(公告)日：2015-04-30

申请号：US14398849

申请日：2013-05-19

申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.

发明人： Shizhen Sun ,  Hao Fang ,  Yong Gu

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/283

CPC分类号： H01L27/1052 ,  H01L21/28273 ,  H01L21/283 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： A NOR flash memory and its manufacturing method are provided in the present disclosure, they are in the field of flash memory. In the manufacturing method, a mask dielectric layer is formed on a second polysilicon layer of a gate stack structure. In addition, part of the mask dielectric layer is etched patternedly to expose part of the second polysilicon layer which is close to a source. Furthermore, the exposed second polysilicon layer is self aligned to form a metal silicide layer. Thus in the NOR flash memory, an unetched mask dielectric layer is substantially located between a metal silicide layer and a drain contacting hole of the NOR flash memory. A drain current between the gate electrode and the drain electrode is small, the above manufacturing method is not complex, a process window is large, a side effect is small, which are advantageous to large scale production.

摘要翻译： 在本公开中提供了NOR闪存及其制造方法，它们在闪存的领域中。 在制造方法中，在栅极堆叠结构的第二多晶硅层上形成掩模电介质层。 此外，掩模介电层的一部分被图案化地蚀刻以暴露靠近源极的第二多晶硅层的部分。 此外，暴露的第二多晶硅层自对准以形成金属硅化物层。 因此，在NOR闪速存储器中，未蚀刻的掩模介电层基本上位于NOR闪存的金属硅化物层和漏极接触孔之间。 栅电极和漏电极之间的漏极电流小，上述制造方法不复杂，工艺窗口大，副作用小，有利于大规模生产。