公开(公告)号：US09580301B2

公开(公告)日：2017-02-28

申请号：US14411537

申请日：2013-06-29

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Dan Dai ,  Xinwei Zhang ,  Guoping Zhou ,  Changfeng Xia

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00825 ,  B81B7/0029 ,  B81C1/0038 ,  B81C2201/0167 ,  B81C2201/053

Abstract: A MEMS chip (100) includes a silicon substrate layer (110), a first oxidation layer (120) and a first thin film layer (130). The silicon substrate layer includes a front surface (112) for a MEMS process and a rear surface (114), both the front surface and the rear surface being polished surfaces. The first oxidation layer is mainly made of silicon dioxide and is formed on the rear surface of the silicon substrate layer. The first thin film layer is mainly made of silicon nitride and is formed on the surface of the first oxidation layer. In the above MEMS chip, by sequentially laminating a first oxidation layer and a first thin film layer on the rear surface of a silicon substrate layer, the rear surface is effectively protected to prevent the scratch damage in the course of a MEMS process. A manufacturing method for the MEMS chip is also provided.

Abstract translation: MEMS芯片（100）包括硅衬底层（110），第一氧化层（120）和第一薄膜层（130）。 硅衬底层包括用于MEMS工艺的前表面（112）和后表面（114），前表面和后表面都是​​抛光表面。 第一氧化层主要由二氧化硅制成，并形成在硅衬底层的后表面上。 第一薄膜层主要由氮化硅制成，并且形成在第一氧化层的表面上。 在上述MEMS芯片中，通过在硅衬底层的后表面依次层叠第一氧化层和第一薄膜层，有效地保护后表面以防止在MEMS工艺过程中的划痕损伤。 还提供了一种用于MEMS芯片的制造方法。

公开(公告)号：US09903884B2

公开(公告)日：2018-02-27

申请号：US14435925

申请日：2013-08-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Meihan Guo ,  Xinwei Zhang ,  Changfeng Xia ,  Wei Su

IPC: G01P15/125 ,  H02N1/08 ,  B81B7/02

CPC classification number: G01P15/125 ,  B81B7/02 ,  G01P2015/0837 ,  H01G5/16 ,  H02N1/08

Abstract: A parallel plate capacitor includes a first polar plate (10), and a second polar plate disposed opposite to the first polar plate (10). The parallel plate capacitor further includes at least a pair of sensitive units disposed on a substrate forming the first polar plate (10); the sensitive units includes sensitive elements (21a, 21b, 22a, 22b) and element connecting arms (23a, 23b, 24a, 24b) connecting the sensitive elements (21a, 21b, 22a, 22b) to the first polar plate (10). The parallel plate capacitor further includes anchoring bases (30, 31, 32, 33) disposed on a substrate where the second polar plate is located; the anchoring bases (30, 31, 32, 33) are connected to the element connecting arms (23a, 23b, 24a, 24b) via cantilever beams (30a, 30b, 31a, 31b, 32a, 32b, 33a, 33b); each element connecting arm (23a, 23b, 24a, 24b) is connected to at least two anchoring bases (30, 31, 32, 33), which are symmetric with respect to the element connecting arm. The parallel plate capacitor is more likely to be influenced by an external factor, thus being more likely to experience capacitance change. An acceleration sensor including the parallel plate capacitor is also provided.

公开(公告)号：US20150233965A1

公开(公告)日：2015-08-20

申请号：US14435925

申请日：2013-08-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Meihan Guo ,  Xinwei Zhang ,  Changfeng Xia ,  Wei Su

IPC: G01P15/125 ,  B81B7/02 ,  H02N1/08

CPC classification number: G01P15/125 ,  B81B7/02 ,  G01P2015/0837 ,  H01G5/16 ,  H02N1/08

Abstract: A parallel plate capacitor includes a first polar plate (10), and a second polar plate disposed opposite to the first polar plate (10). The parallel plate capacitor further includes at least a pair of sensitive units disposed on a substrate forming the first polar plate (10); the sensitive units includes sensitive elements (21a, 21b, 22a, 22b) and element connecting arms (23a, 23b, 24a, 24b) connecting the sensitive elements (21a, 21b, 22a, 22b) to the first polar plate (10). The parallel plate capacitor further includes anchoring bases (30, 31, 32, 33) disposed on a substrate where the second polar plate is located; the anchoring bases (30, 31, 32, 33) are connected to the element connecting arms (23a, 23b, 24a, 24b) via cantilever beams (30a, 30b, 31a, 31b, 32a, 32b, 33a, 33b); each element connecting arm (23a, 23b, 24a, 24b) is connected to at least two anchoring bases (30, 31, 32, 33), which are symmetric with respect to the element connecting arm. The parallel plate capacitor is more likely to be influenced by an external factor, thus being more likely to experience capacitance change. An acceleration sensor including the parallel plate capacitor is also provided.

Abstract translation: 平行板电容器包括第一极板（10）和与第一极板（10）相对设置的第二极板。 平行板电容器还包括至少一对设置在形成第一极板（10）的基板上的敏感单元。 敏感单元包括将敏感元件（21a，21b，22a，22b）连接到第一极板（10）的敏感元件（21a，21b，22a，22b）和元件连接臂（23a，23b，24a，24b）。 平行板电容器还包括设置在第二极板所在的基板上的固定基座（30,31,32,33）。 通过悬臂梁（30a，30b，31a，31b，32a，32b，33a，33b）将锚定基座（30,31,32,33）连接到元件连接臂（23a，23b，24a，24b） 每个元件连接臂（23a，23b，24a，24b）连接到至少两个相对于元件连接臂对称的锚定基座（30,31,32,33）。 并联平板电容更可能受到外部因素的影响，因此更容易发生电容变化。 还提供了包括平行板电容器的加速度传感器。

公开(公告)号：US20150175409A1

公开(公告)日：2015-06-25

申请号：US14411989

申请日：2013-08-19

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Xinwei Zhang ,  Dan Dai ,  Guoping Zhou ,  Changfeng Xia

IPC: B81C1/00

CPC classification number: B81C1/0038 ,  B81B2203/0127 ,  B81C1/00158 ,  B81C1/00531

Abstract: Provided is a method for fabricating a multi-trench structure, including steps of: performing anisotropic etching on a semiconductor substrate so as to form a vertical trench; growing a first epitaxial layer on the semiconductor substrate in which the vertical trench has been formed, so that the first epitaxial layer covers the top of the vertical trench to form a closed structure; performing anisotropic and isotropic etching on the closed structure, so as to form a trench array, and to make the trench array communicate with the vertical trench, the trench array including a number of trenches or vias, upper portions of a number of trenches or vias being separated from each other, and lower portions thereof communicating with each other to form a cavity; and growing a second epitaxial layer to cover the trench array, so as to form a closed multi-trench structure. With two times of growth of the epitaxial layers, the multi-trench structure remains stable and solid in a fabricating process, which prevents phenomena of film breakage or falling off in the fabricating process.

Abstract translation: 提供一种制造多沟槽结构的方法，包括以下步骤：在半导体衬底上进行各向异性蚀刻以形成垂直沟槽; 在其上形成有垂直沟槽的半导体衬底上生长第一外延层，使得第一外延层覆盖垂直沟槽的顶部以形成闭合结构; 在闭合结构上执行各向异性和各向同性蚀刻，以便形成沟槽阵列，并且使沟槽阵列与垂直沟槽连通，沟槽阵列包括多个沟槽或通孔，多个沟槽或通孔的上部 彼此分离，并且其下部彼此连通以形成空腔; 以及生长第二外延层以覆盖沟槽阵列，以便形成封闭的多沟槽结构。 通过外延层的两次生长，多沟槽结构在制造过程中保持稳定和稳定，这防止了制造过程中膜断裂或脱落的现象。

公开(公告)号：US10077188B2

公开(公告)日：2018-09-18

申请号：US15405603

申请日：2017-01-13

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Dan Dai ,  Xinwei Zhang ,  Guoping Zhou ,  Changfeng Xia

IPC: B81C1/00

CPC classification number: B81C1/00825 ,  B81B7/0029 ,  B81C1/0038 ,  B81C2201/0167 ,  B81C2201/053

Abstract: A method of manufacturing a MEMS chip includes: providing a silicon substrate layer, the silicon substrate layer comprising a front surface configured to perform a MEMS process and a rear surface opposite to the front surface; growing a first oxidation layer mainly made of SiO2 on the rear surface of the silicon substrate layer by performing a thermal oxidation process; and depositing a first thin film layer mainly made of silicon nitride on the first oxidation layer by performing a low pressure chemical vapor deposition process.

公开(公告)号：US09006867B2

公开(公告)日：2015-04-14

申请号：US14364933

申请日：2012-11-20

Applicant: CSMC Technologies FAB1 Co., Ltd.

Inventor： Xinwei Zhang ,  Changfeng Xia ,  Chengjian Fan ,  Wei Su

IPC: H01L21/66 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L22/30 ,  H01L21/30608 ,  H01L21/3083 ,  H01L22/12

Abstract: A monitoring structure and a relevant monitoring method for the silicon wet etching depth are provided. The structure includes a wet etched groove formed on a monocrystalline silicon material with at least two top surfaces thereof being rectangular; and the top surface widths of the grooves are Wu and W1 respectively, Wu=du/0.71, and W1=du/0.71, where du is the maximum wet etching depth to be monitored, and d1 is the minimum of the wet etching depth to be monitored. The method includes: performing anisotropic wet etching on a monocrystalline silicon wafer according to a pattern with a monitoring pattern, forming an etched groove to be monitored and a structure for monitoring the depth of the groove, and then monitoring the structure to monitor the wet etching depth. The etching depth of the groove can be monitored with low costs, and a higher monitoring accuracy is obtained.

Abstract translation: 提供了硅湿蚀刻​​深度的监测结构和相关监测方法。 该结构包括形成在单晶硅材料上的湿蚀刻槽，其至少两个顶表面是矩形; 并且槽的顶面宽度分别为Wu和W1，Wu = du / 0.71，W1 = du / 0.71，其中du是要监测的最大湿蚀刻深度，d1是湿蚀刻深度的最小值 被监视。 该方法包括：根据具有监测图案的图案在单晶硅晶片上进行各向异性湿蚀刻，形成待监测的蚀刻凹槽和用于监测凹槽深度的结构，然后监测结构以监测湿蚀刻 深度。 可以以低成本监测凹槽的蚀刻深度，并且获得更高的监视精度。

公开(公告)号：US20140346647A1

公开(公告)日：2014-11-27

申请号：US14364933

申请日：2012-11-20

Applicant: CSMC TECHNOLOGIES FAB1 CO.,LTD

Inventor： Xinwei Zhang ,  Changfeng Xia ,  Chengjian Fan ,  Wei Su

IPC: H01L21/66 ,  H01L21/308

CPC classification number: H01L22/30 ,  H01L21/30608 ,  H01L21/3083 ,  H01L22/12

Abstract: A monitoring structure and a relevant monitoring method for the silicon wet etching depth are provided. The structure includes a wet etched groove formed on a monocrystalline silicon material with at least two top surfaces thereof being rectangular; and the top surface widths of the grooves are Wu and Wl respectively, Wu=du/0.71, and Wl=du/0.71, where du is the maximum wet etching depth to be monitored, and dl is the minimum of the wet etching depth to be monitored. The method includes: performing anisotropic wet etching on a monocrystalline silicon wafer according to a pattern with a monitoring pattern, forming an etched groove to be monitored and a structure for monitoring the depth of the groove, and then monitoring the structure to monitor the wet etching depth. The etching depth of the groove can be monitored with low costs, and a higher monitoring accuracy is obtained.

Abstract translation: 提供了硅湿蚀刻​​深度的监测结构和相关监测方法。 该结构包括形成在单晶硅材料上的湿蚀刻槽，其至少两个顶表面是矩形; 并且槽的顶面宽度分别为Wu和Wl，Wu = du / 0.71，Wl = du / 0.71，其中du是要监测的最大湿蚀刻深度，d1是湿蚀刻深度的最小值 被监视。 该方法包括：根据具有监测图案的图案在单晶硅晶片上进行各向异性湿蚀刻，形成待监测的蚀刻凹槽和用于监测凹槽深度的结构，然后监测结构以监测湿蚀刻 深度。 可以以低成本监测凹槽的蚀刻深度，并且获得更高的监视精度。