公开(公告)号：US20240222473A1

公开(公告)日：2024-07-04

申请号：US18684175

申请日：2022-12-20

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Feng LIN ,  Chaoqi XU ,  Shuxian CHEN ,  Chunxu LI ,  Li LU ,  Siyang LIU ,  Weifeng SUN

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66734 ,  H01L21/2251 ,  H01L29/0619 ,  H01L29/41741 ,  H01L29/7813

Abstract: The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.

公开(公告)号：US20240047212A1

公开(公告)日：2024-02-08

申请号：US18258902

申请日：2021-07-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Hongfeng JIN ,  Ruibin CAO ,  Feng LIN ,  Xiang QIN ,  Yu HUANG ,  Chunxu LI

IPC: H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L21/027 ,  H01L21/266

CPC classification number: H01L21/2652 ,  H01L29/66681 ,  H01L29/7816 ,  H01L21/0274 ,  H01L21/266

Abstract: A semiconductor device and a manufacturing method therefor are disclosed. The method includes: providing a substrate of a first conductivity type; forming doped regions of a second conductivity type in the substrate, the doped regions including adjacent first and second drift regions, wherein the second conductivity type is opposite to the first conductivity type; forming a polysilicon film on the substrate, the polysilicon film covering the doped regions; forming patterned photoresist on the polysilicon film, which covers the first and second drift regions, and in which the polysilicon film above a reserved region for a body region between the first and second drift regions is exposed; and forming the body region of the first conductivity type in the reserved region by performing a high-energy ion implantation process, the body region having a top surface that is flush with top surfaces of the doped regions, the body region having a bottom surface that is not higher than bottom surfaces of the doped regions. The problem of morphological changes possibly experienced by the photoresist due to a high temperature in an etching process, which may lead to an impaired effect of the high-energy ion implantation process, can be circumvented.

公开(公告)号：US20220262948A1

公开(公告)日：2022-08-18

申请号：US17631287

申请日：2020-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Chunxu LI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40

Abstract: The present invention relates to an LDMOS device and a method for preparing same. When a field plate hole is formed by etching an interlayer dielectric layer, the etching of the field plate hole is stopped on a blocking layer by means of providing the blocking layer between a semiconductor base and the interlayer dielectric layer. Since the blocking layer is provided with at least one layer of an etch stop layer, and steps are formed on the surface of the blocking layer, at least two levels of formed hole field plates are distributed in a step shape, and lower ends of the first level of hole field plates to the nth level of hole field plates are gradually further away from the drift area in the direction from a gate structure to a drain area.