公开(公告)号：US20200328689A1

公开(公告)日：2020-10-15

申请号：US16915524

申请日：2020-06-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Shen XU ,  Wei WANG ,  Feng LIN ,  Boyong HE ,  Wei SU ,  Weifeng SUN ,  Longxing SHI

IPC: H02M3/335 ,  G01R19/165 ,  H03K5/24

Abstract: Provided is a dynamic control method that turns off a primary-side switching transistor when an output voltage exceeds an upper limit, and control the switching of a secondary-side synchronous rectification transistor with a fixed cycle and a fixed duty cycle. During the time that the synchronous rectification transistor is turned on, the energy of a load capacitor at the output end is extracted to the primary side, which causes the output voltage to drop rapidly and the overshoot voltage to decrease greatly.

公开(公告)号：US20220115532A1

公开(公告)日：2022-04-14

申请号：US17417677

申请日：2019-12-23

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Weifeng SUN ,  Rongcheng LOU ,  Kui XIAO ,  Feng LIN ,  Jiaxing WEI ,  Sheng LI ,  Siyang LIU ,  Shengli LU ,  Longxing SHI

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L21/04 ,  H01L29/66

Abstract: A power semiconductor device includes a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.

公开(公告)号：US20240339522A1

公开(公告)日：2024-10-10

申请号：US18292067

申请日：2022-12-01

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chaoqi XU ,  Shuxian CHEN ,  Chunxia MA ,  Yi ZHANG ,  Penglong XU ,  Feng LIN ,  Ruibin CAO

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/66681 ,  H01L29/402 ,  H01L29/7816

Abstract: In a manufacturing method for an LDMOS integrated device, a provided semiconductor substrate has an NLDMOS area and a PLDMOS area; then a dielectric layer on the NLDMOS area and a dielectric layer on the PLDMOS area are formed on the semiconductor substrate, and a stress material layer is formed on the dielectric layer on the NLDMOS area and/or on the dielectric layer on the PLDMOS area, the thickness of the dielectric layer on the NLDMOS region being greater than the thickness of the dielectric layer on the PLDMOS region; then heat treatment is performed to adjust the stress of the stress material layer, so as to improve the electron mobility of a device; then the stress material layer is removed.

公开(公告)号：US20240222473A1

公开(公告)日：2024-07-04

申请号：US18684175

申请日：2022-12-20

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Feng LIN ,  Chaoqi XU ,  Shuxian CHEN ,  Chunxu LI ,  Li LU ,  Siyang LIU ,  Weifeng SUN

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66734 ,  H01L21/2251 ,  H01L29/0619 ,  H01L29/41741 ,  H01L29/7813

Abstract: The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.

公开(公告)号：US20220367722A1

公开(公告)日：2022-11-17

申请号：US17767333

申请日：2020-08-26

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Wangran WU ,  Guangan YANG ,  Feng LIN ,  Guipeng SUN ,  Yaohui WANG ,  Weifeng SUN ,  Longxing SHI

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: An IGZO thin-film transistor and a method for manufacturing same. The method comprises: acquiring a substrate; forming an IGZO layer on the substrate by means of a solution process; doping V impurities on a surface of the IGZO layer by means of a spin doping process; forming a source electrode at one side of the IGZO layer, and forming a drain electrode at the other side thereof; forming a gate dielectric layer on the doped IGZO layer; and forming a gate electrode on the gate dielectric layer.

公开(公告)号：US20250056834A1

公开(公告)日：2025-02-13

申请号：US18722930

申请日：2022-11-30

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO LTD.

Inventor： Long ZHANG ,  Nailong HE ,  Yongjiu CUI ,  Sen ZHANG ,  Xiaona WANG ,  Feng LIN ,  Jie MA ,  Siyang LIU ,  Weifeng SUN

IPC: H01L29/78 ,  H01L21/266 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: A manufacturing method for a P-type laterally diffused metal oxide semiconductor device includes: forming a N-type buried layer in a substrate, forming a P-type region located on the N-type buried layer, and forming a mask layer located on the P-type region; patterning the mask layer to form at least two injection windows; performing N-type ion implantation by the at least two injection windows; forming an oxide layer; removing the mask layer; performing P-type ion implantation on the P-type region to form a P-type doped region; diffusing the P-type doped region to form a drift region and two P-type well regions, diffusing the high-voltage N-well doped region to form a high-voltage N-type well region, and diffusing the low-voltage N-well doped region to form a low-voltage N-type well region; and forming a source doped region, a drain doped region, and a gate.

公开(公告)号：US20240047212A1

公开(公告)日：2024-02-08

申请号：US18258902

申请日：2021-07-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Hongfeng JIN ,  Ruibin CAO ,  Feng LIN ,  Xiang QIN ,  Yu HUANG ,  Chunxu LI

IPC: H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L21/027 ,  H01L21/266

CPC classification number: H01L21/2652 ,  H01L29/66681 ,  H01L29/7816 ,  H01L21/0274 ,  H01L21/266

Abstract: A semiconductor device and a manufacturing method therefor are disclosed. The method includes: providing a substrate of a first conductivity type; forming doped regions of a second conductivity type in the substrate, the doped regions including adjacent first and second drift regions, wherein the second conductivity type is opposite to the first conductivity type; forming a polysilicon film on the substrate, the polysilicon film covering the doped regions; forming patterned photoresist on the polysilicon film, which covers the first and second drift regions, and in which the polysilicon film above a reserved region for a body region between the first and second drift regions is exposed; and forming the body region of the first conductivity type in the reserved region by performing a high-energy ion implantation process, the body region having a top surface that is flush with top surfaces of the doped regions, the body region having a bottom surface that is not higher than bottom surfaces of the doped regions. The problem of morphological changes possibly experienced by the photoresist due to a high temperature in an etching process, which may lead to an impaired effect of the high-energy ion implantation process, can be circumvented.

公开(公告)号：US20220384641A1

公开(公告)日：2022-12-01

申请号：US17886609

申请日：2022-08-12

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Guipeng SUN ,  Feng LIN ,  Shuxian CHEN

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/266

Abstract: A method for manufacturing a semiconductor device, and a semiconductor device. The method includes: providing a semiconductor substrate of a first conductivity type, forming a deep well of a second conductivity type in the semiconductor substrate, forming a channel region of the first conductivity type, a first well region of the first conductivity type, and a drift region of the second conductivity type in the deep well, the first well region and the channel region being spaced by a portion of the deep well, the drift region being located between the channel region and the first well region, forming an ion implantation region of the first conductivity type in the deep well, the ion implantation region being located under the drift region, and forming a source region of the second conductivity type and a drain region of the second conductivity type in the deep well.

公开(公告)号：US20200336076A1

公开(公告)日：2020-10-22

申请号：US16959116

申请日：2018-12-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Qinsong QIAN ,  Shengyou XU ,  Feng LIN ,  Hao WANG ,  Wei SU ,  Qi LIU ,  Longxing SHI

IPC: H02M3/335

Abstract: A control system for synchronous rectifying transistor of LLC converter, the system comprising a voltage sampling circuit, a high-pass filtering circuit, a PI compensation and effective value detection circuit, and a control system taking a microcontroller (MCU) as a core. When the LLC converter is operating at a high frequency, a drain-source voltage VDS(SR) of the synchronous rectifying transistor delivers, via the sampling circuit, a change signal of the drain-source voltage during turn-off into the high-pass filtering circuit and the PI compensation and effective value detection circuit to obtain an effective value amplification signal of a drain-source voltage oscillation signal caused by parasitic parameters, and the current value is compared with a previously collected value via a control circuit taking a microcontroller (MCU) as a core, so as to change a turning-on time of the synchronous rectifying transistor in the next period.

公开(公告)号：US20180130877A1

公开(公告)日：2018-05-10

申请号：US15564181

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Feng HUANG ,  Guangtao HAN ,  Guipeng SUN ,  Feng LIN ,  Longjie ZHAO ,  Huatang LIN ,  Bing ZHAO

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L29/66681 ,  H01L29/7816

Abstract: Provided are a laterally diffused metal oxide semiconductor field-effect transistor and a manufacturing method therefor. The method comprises: providing a wafer on which a first N well (22), a first P well (24) and a channel region shallow trench isolating structure (42) are formed; forming a high-temperature oxidation film on the surface of the wafer by deposition; photoetching and dryly etching the high-temperature oxidation film, and reserving a thin layer as an etching buffer layer; performing wet etching, removing the etching buffer layer in a region which is not covered by a photoresist, and forming a mini oxidation layer (52); performing photoetching and ion injection to form a second N well (32) in the first N well and form a second P well (34) in the first P well; forming a polysilicon gate (62) and a gate oxide layer on the surface of the wafer; and photoetching and injecting N-type ions to form a drain electrode (72) and a source electrode (74).