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公开(公告)号：US20180175804A1
公开(公告)日：2018-06-21
申请号：US15565191
申请日：2016-01-29
发明人： Xueyan WANG , Weiyan ZHANG , Qiang CHEN
CPC分类号： H03F1/26 , H03F3/45475 , H03F2200/165 , H03F2203/45514
摘要： A signal amplification circuit comprises a low pass filter circuit (100). The low pass filter circuit (100) comprises two input ends and two output ends and further comprises two capacitors (C1, C2) having opposite polarities respectively connected between two output ends. A buffer circuit (200) comprises two input ends, a first operational amplifier (A1) and a second operational amplifier (A2), two output ends and a plurality of switches. A switched capacitor integrated circuit (300) comprises two input ends, a third operational amplifier (A3), a plurality of capacitor modules, a plurality of chopper modulators and two output ends. A signal switch (S) is used to control the on and off states of voltage signal before amplification.
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公开(公告)号：US20190238122A1
公开(公告)日：2019-08-01
申请号：US16312345
申请日：2017-06-21
发明人： Xueyan WANG , Qiang CHEN
摘要： A ring voltage control oscillator includes: a conversion unit (100), cascaded multistage delay units (200) and cascaded multistage isolation buffer units (300). The conversion unit (100) receives a voltage signal controlled by the external, converts the voltage signal into a current signal and respectively transmits the current signal to a plurality of delay units (200) and a plurality of isolation buffer units (300). The delay unit (200) comprises two signal input terminals and two signal output terminals; the isolation buffer unit (300) comprises two signal input terminals and two signal output terminals; a first signal input terminal and a second signal input terminal of the isolation buffer unit (300) are correspondingly connected to a first signal output terminal and a second signal output terminal of the same stage of the delay unit (200), respectively; clock signals outputted by first signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference; clock signals outputted by the second signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference.
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公开(公告)号：US20180224281A1
公开(公告)日：2018-08-09
申请号：US15747882
申请日：2016-05-11
发明人： Huagang WU , Xueyan WANG
IPC分类号： G01C19/5776 , G01P15/12 , G01P15/18
CPC分类号： G01C19/5776 , G01P15/0802 , G01P15/12 , G01P15/18 , G05B2219/36159
摘要： An accelerator comprises: an accelerometer (100), configured to detect an acceleration of a motion of a carrier and output a corresponding electrical signal; a sampling and low-pass filter (200), coupled to the accelerometer (100), and configured to sample the electrical signal regularly and filter a noise from the electrical signal; an amplifier (300), configured to amplify the electrical signal after filtering the noise; an analog-to-digital converter (400), configured to convert the amplified electrical signal into a digital signal; a function control module (500), configured to process the digital signal and output a control signal to control the analog-to-digital converter (400), the amplifier (300), and the sampling and low-pass filter (200); and an oscillator module (600), configured to output, according to the control signal, a sampling signal to the sampling and low-pass filter (200), so as to control the sampling and low-pass filter (200) to sample the electrical signal regularly.
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公开(公告)号：US20180375521A1
公开(公告)日：2018-12-27
申请号：US15741448
申请日：2016-05-10
发明人： Xueyan WANG , Ying YANG , Jingjia YU
IPC分类号： H03L7/081
CPC分类号： H03L7/0812 , H03L7/00 , H03L7/08
摘要： A delay locked loop detection system (10), the system can be used for detecting the working state of a delay locked loop (400) and comprises: a signal generator (300), which is used for generating a reference clock and providing the reference clock to the delay locked loop (400); and a testing instrument (500), which is used for acquiring the clock signals output from the delay locked loop (400) and measuring whether the time delays thereof are consistent with expectations; the detection system (10) further comprises at least one of the following circuits: a pre-receiving circuit (100), which is used for receiving the reference clock from the signal generator (300) and amplifying and shaping the reference clock and then providing the reference clock to the delay locked loop (400); and a multiphase multiplexing circuit (200), which is used for receiving the clock signals output from the delay locked loop (400) and synthesizing and then providing a plurality of clock signals with different delay to the testing instrument (500). Also included is a delay locked loop detection method. The system and method mentioned above enable an accurate measurement for the delays of the delay locked loop.
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