公开(公告)号：US20170047273A1

公开(公告)日：2017-02-16

申请号：US15334308

申请日：2016-10-26

Applicant: CYNTEC CO., LTD.

Inventor： BAU-RU LU ,  JENG-JEN LI ,  KUN-HONG SHIH ,  KAIPENG CHIANG

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/49537 ,  H01L21/563 ,  H01L23/13 ,  H01L23/49506 ,  H01L23/49534 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15321 ,  H05K1/021 ,  H05K1/186 ,  Y10T29/49124 ,  H01L2924/00

Abstract: The invention discloses a package structure made of the combination of a device carrier and a modifiable substrate. In one embodiment, a recess is formed in the device carrier and a conductive element is disposed on the substrate, wherein the substrate is disposed on the device carrier and the conductive element is located in the recess of the device carrier. The conductive pattern in the substrate is electrically connected to the device carrier and I/O terminals of the first conductive element. The invention also discloses a method for manufacturing a package structure made of the combination of a device carrier and a modifiable substrate. In one embodiment, a portion of the conductive pattern in the substrate can be modified.

Abstract translation: 本发明公开了一种由装置载体和可修改基底的组合制成的封装结构。 在一个实施例中，在器件载体中形成凹部，并且导电元件设置在衬底上，其中衬底设置在器件载体上，并且导电元件位于器件载体的凹部中。 衬底中的导电图案电连接到器件载体和第一导电元件的I / O端子。 本发明还公开了一种用于制造由器件载体和可修改基底的组合制成的封装结构的方法。 在一个实施例中，衬底中的导电图案的一部分可以被修改。