公开(公告)号：US11983538B2

公开(公告)日：2024-05-14

申请号：US17659569

申请日：2022-04-18

Applicant: Cadence Design Systems, Inc.

Inventor： Robert T. Golla ,  Ajay A. Ingle

IPC: G06F9/38 ,  G06F12/0855

CPC classification number: G06F9/3834 ,  G06F12/0855

Abstract: Techniques are disclosed relating to a processor load-store unit. In some embodiments, the load-store unit is configured to execute load/store instructions in parallel using first and second pipelines and first and second tag memory arrays. In tag write conflict situations, the load-store unit may arbitrate between the first and second pipelines to ensure the first and second tag memory array contents remain identical. In some embodiments, a data cache tag replay scheme is utilized. In some embodiments, executing load/store instructions in parallel with fills, probes, and store-updates, using separate but identical tag memory arrays, may advantageously improve performance.

公开(公告)号：US20230333856A1

公开(公告)日：2023-10-19

申请号：US17659569

申请日：2022-04-18

Applicant: Cadence Design Systems, Inc

Inventor： Robert T. Golla ,  Ajay A. Ingle

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0673 ,  G06F3/0604

Abstract: Techniques are disclosed relating to a processor load-store unit. In some embodiments, the load-store unit is configured to execute load/store instructions in parallel using first and second pipelines and first and second tag memory arrays. In tag write conflict situations, the load-store unit may arbitrate between the first and second pipelines to ensure the first and second tag memory array contents remain identical. In some embodiments, a data cache tag replay scheme is utilized. In some embodiments, executing load/store instructions in parallel with fills, probes, and store-updates, using separate but identical tag memory arrays, may advantageously improve performance.