公开(公告)号：US20240296269A1

公开(公告)日：2024-09-05

申请号：US18178463

申请日：2023-03-03

Applicant: Cadence Design Systems, Inc.

Inventor： Mitchell G. Poplack ,  Bhoumik Shah ,  Jennifer Lee

IPC: G06F30/3308

CPC classification number: G06F30/3308

Abstract: The systems and methods described herein include emulators that implement wrappers comprising instrumentation logic for the emulator components (e.g., memories) to perform certain memory-related functions. These functions allow the physical binary memories of the emulator to behave as a ternary memory. The memory wrappers include instrumentation logic around logic of the physical binary memories. In some cases, embodiments generate the wrappers for the user memory, rather than performing conventional synthesis functions for user-design memories. The inputs include the user ternary RTL, as well as additional potential inputs for pre-compiler control. The wrappers instantiate the operations, such as MPRs or MPWs, and create the ternary-memory support logic to, for example, prevent unknown-value writes and to output unknown values X for unknown-value reads.

公开(公告)号：US11308008B1

公开(公告)日：2022-04-19

申请号：US17139333

申请日：2020-12-31

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Christian Wiencke ,  Bhoumik Shah ,  Ping-Sheng Tseng

IPC: G06F13/16 ,  G06F9/455 ,  G06F13/28

Abstract: Embodiments described herein provide for an emulation system that supports efficiently generating outgoing messages to a test bench. The emulation system transmits the outgoing messages to the test bench various busses and interfaces. The compiled virtual logic writes the outgoing messages into memories of the emulation chips for queuing, and notification messages associated with the queued outgoing messages. A traffic processor transfers from memories to the test bench using buses and interfaces. The traffic processor reads a notification message from memory to identify the storage location with a corresponding queued outgoing message. The traffic processor then transmits DMA requests to I/O components (e.g., DMA engines) to instruct the I/O components to transfer the queued outgoing message to the host device.