公开(公告)号：US10289775B1

公开(公告)日：2019-05-14

申请号：US15694309

申请日：2017-09-01

Applicant: Cadence Design Systems, Inc.

Inventor： Brian Wilson ,  Charles Jay Alpert ,  Zhuo Li

IPC: G06F17/50

Abstract: Various embodiments described herein assign, within a circuit design, a clock tap to a clock device (e.g., flip-flop) to improve timing of a path between the clock tap and the clock device. In particular, some embodiments identify which clock devices should be assigned to a clock tap so as to improve final timing as seen under an on-chip variation timing analysis, such an AOCV/CPPR (advanced on-chip variation/common clock path pessimism removal) timing analysis. Some such embodiments may achieve this by identifying, after post-route-optimization, critical clock-tap-to-clock-device assignments based on timing analysis results (e.g., from AOCV/CPPR timing analysis) and feeding back those critical clock-tap-to-clock-device assignments to a process performing new clock tap assignments.

公开(公告)号：US10095824B1

公开(公告)日：2018-10-09

申请号：US15293010

申请日：2016-10-13

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Zhuo Li ,  Wen-Hao Liu ,  Charles Alpert ,  Brian Wilson

IPC: G06F17/00 ,  G06F17/50

Abstract: Disclosed herein are systems and methods to construct a symmetric clock-distribution H-tree in upper layers of an integrated circuit (IC), which may have complicated routing and/or placement blockages. The systems and methods disclosed herein may implement concomitant bottom-up wiring and top-down rewiring to achieve a clock-distribution tree symmetrically balanced across all of the hierarchical levels while respecting the complicated routing and/or placement blockages. Such symmetrically balanced clock-tree ensures that a clock-signal reaches all of the clock-sinks simultaneously or near simultaneously thereby minimizing clock-skew across the clock-sinks. The minimal skew symmetric clock-distribution H-tree may therefore be used for higher performance and high speed ICs.

公开(公告)号：US10216880B1

公开(公告)日：2019-02-26

申请号：US15212002

申请日：2016-07-15

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Wen-Hao Liu ,  Zhuo Li ,  Charles Alpert ,  Brian Wilson

IPC: G06F17/50

Abstract: Methods and systems of optimization of and Integrated Circuit (IC) design disclosed herein result in a power efficient clustering of circuit devices. The methods may depart from the conventional geometric clustering using a nearest neighbor approach when wiring flops to local clock buffers. To reduce the number of clock-gaters, the methods in one embodiment use a grouping of flops wired to a common clock-gater to form nodes, which are then wired to the local clock buffers based on a load-balancing process. In another embodiment, the methods use a local cleanup process to rewire the nodes between neighboring clock buffers to further reduce the amount of clock-gaters.