公开(公告)号：US11023636B1

公开(公告)日：2021-06-01

申请号：US15931547

申请日：2020-05-13

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Ratnakar Goyal ,  Manuj Verma ,  Harmandeep Singh

IPC: G06F30/3312 ,  G06F119/02

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a susceptibility window. These techniques identify a set of multiple aggressors in an electronic design and determine, at a susceptibility window module stored in memory and executing in conjunction with a microprocessor of a computing node, a susceptibility window for an internal node of a victim and a timing window for the set of multiple aggressors in the electronic design. These techniques further determine a subset having at least one aggressor using at least the susceptibility window of the victim and the timing window for the set of multiple aggressors, and determine whether a glitch in the electronic design causes a violation at the internal node of the electronic design based at least in part upon the timing window and the susceptibility.