公开(公告)号：US10289774B1

公开(公告)日：2019-05-14

申请号：US15474733

申请日：2017-03-30

Applicant: Cadence Design Systems, Inc.

Inventor： Pradeep Yadav ,  Ratnakar Goyal ,  Prashant Sethia ,  Manuj Verma

IPC: G06F17/50

Abstract: Various embodiments describe performing static timing analysis (STA) on a circuit design such that delay timing calculation results generated by an STA on the circuit design can be reused by subsequent STAs on the circuit design in place of performing a set of delay timing calculations on the circuit design.

公开(公告)号：US11023636B1

公开(公告)日：2021-06-01

申请号：US15931547

申请日：2020-05-13

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Ratnakar Goyal ,  Manuj Verma ,  Harmandeep Singh

IPC: G06F30/3312 ,  G06F119/02

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a susceptibility window. These techniques identify a set of multiple aggressors in an electronic design and determine, at a susceptibility window module stored in memory and executing in conjunction with a microprocessor of a computing node, a susceptibility window for an internal node of a victim and a timing window for the set of multiple aggressors in the electronic design. These techniques further determine a subset having at least one aggressor using at least the susceptibility window of the victim and the timing window for the set of multiple aggressors, and determine whether a glitch in the electronic design causes a violation at the internal node of the electronic design based at least in part upon the timing window and the susceptibility.

公开(公告)号：US09589096B1

公开(公告)日：2017-03-07

申请号：US14716059

申请日：2015-05-19

Applicant: Cadence Design Systems, Inc.

Inventor： Umesh Gupta ,  Vishnu Kumar ,  Manish Bansal ,  Naresh Kumar ,  Manuj Verma ,  Prashant Sethia

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F2217/84

Abstract: Methods and systems provide setup and generation of SPICE results for a set of timing path(s) and integration of SPICE simulation with static timing analysis (STA) path-based results generation. In an embodiment, a method may select a candidate set of timing paths, perform path based analysis (PBA) on the selected paths, generate SPICE results for the selected paths, and render the PBA and SPICE results in an integrated user interface to facilitate sign off based on annotated constraints and correlation between STA results and SPICE results. Methods and systems of the present disclosure find application in, among other things, timing signoff in an electronic design and verification process.

Abstract translation: 方法和系统提供SPICE结果的设置和生成，用于一组定时路径以及SPICE仿真与静态时序分析（STA）基于路径的结果生成的集成。 在一个实施例中，方法可以选择候选的定时路径集合，在所选择的路径上执行基于路径的分析（PBA），为所选择的路径生成SPICE结果，并将PBA和SPICE结果呈现在集成的用户界面中以便于签名 基于注释约束和STA结果与SPICE结果之间的相关性。 本公开的方法和系统尤其涉及在电子设计和验证过程中的定时签发。

公开(公告)号：US09529962B1

公开(公告)日：2016-12-27

申请号：US14732160

申请日：2015-06-05

Applicant: Cadence Design Systems, Inc.

Inventor： Amit Dhuria ,  Pradeep Yadav ,  Manuj Verma ,  Naresh Kumar ,  Prashant Sethia

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/84

Abstract: The present disclosure relates to a computer-implemented method for use with an electronic design. Embodiments include identifying, using one or more processors, a plurality of sibling nets associated with the electronic design and determining if the plurality of sibling nets have a same input slew rate. If the plurality of sibling nets do not have a same input slew rate, embodiments also include determining a delay calculation (DC) for each of the plurality of sibling nets. If the plurality of sibling nets do have a same input slew rate, embodiments further include sharing a stored DC with the plurality of sibling nets.

Abstract translation: 本公开涉及一种用于电子设计的计算机实现的方法。 实施例包括使用一个或多个处理器识别与电子设计相关联的多个兄弟网，并确定多个兄弟网是否具有相同的输入转换速率。 如果多个兄弟网不具有相同的输入压摆率，则实施例还包括确定多个兄弟网中的每一个的延迟计算（DC）。 如果多个兄弟网确实具有相同的输入转换速率，则实施例还包括与多个兄弟网共享存储的DC。

公开(公告)号：US10031986B1

公开(公告)日：2018-07-24

申请号：US15086654

申请日：2016-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Vishnu Kumar ,  Manuj Verma

IPC: G06F17/50

Abstract: The present disclosure relates to a system and method for performing Path-Based Analysis (PBA) of an electronic circuit design. Embodiments may include receiving a command to create a spice deck of a timing path associated with the electronic circuit design. In response to receiving the command, embodiments may further include initiating PBA for the timing path and identifying one or more stages within the timing path. Embodiments may also include performing a delay calculation for each of the one or more stages and generating a stage spice deck for each of the one or more stages based upon, at least in part, information from the delay calculation, wherein the stage spice deck encapsulates all elements of the stage. Embodiments may further include connecting the stage spice deck for each of the one or more stages in series to form a complete path spice deck.

公开(公告)号：US09881123B1

公开(公告)日：2018-01-30

申请号：US15198635

申请日：2016-06-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Ratnakar Goyal ,  Manuj Verma ,  Igor Keller ,  Arvind Nembili Veeravalli

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5031 ,  G06F2217/82

Abstract: A method and system are provided for timing analysis of an electronic circuit design. A timing graph defines a plurality of timing paths through different subsections of the electronic circuit design. A timing window is defined for each of the nodes included in a timing path. At least one preliminary round of a predetermined signal integrity analysis is executed on the circuit design based on the timing windows to identify at least one pair of crosstalk-coupled victim and aggressor nodes. Each victim node's timing window is adaptively adjusted according to a predetermined timing property thereof. At least one primary round of the predetermined signal integrity analysis is executed on the electronic circuit design based in part on this adaptively adjusted timing window for each victim node to generate a delay, which is annotated to the timing graph. A predetermined static timing analysis is executed based on the delay-annotated timing graph.