公开(公告)号：US09633163B1

公开(公告)日：2017-04-25

申请号：US14589537

申请日：2015-01-05

Applicant: Cadence Design Systems, Inc.

Inventor： Hitesh Mohan Kumar ,  Sagar Kumar ,  Ankur Gupta

IPC: G06F17/50 ,  H01L23/498 ,  H01L27/02 ,  H01L21/66 ,  G06F9/44 ,  G06F17/30

CPC classification number: G06F17/5077 ,  G06F8/71 ,  G06F17/30867 ,  G06F17/5045 ,  G06F17/5081 ,  G06F17/509 ,  G06F2217/06 ,  H01L22/34 ,  H01L23/49838 ,  H01L27/0207

Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. The method may include providing, using one or more processors, an electronic design and visually displaying a plurality of possible route sets associated with the electronic design at a graphical user interface. The method may include providing an option to select between the plurality of possible route sets at the graphical user interface.

公开(公告)号：US11941334B1

公开(公告)日：2024-03-26

申请号：US17665670

申请日：2022-02-07

Applicant: Cadence Design Systems, Inc.

Inventor： Deepak Gupta ,  Hitesh Mohan Kumar ,  Yatinder Singh

IPC: G06F30/31 ,  G06F30/39 ,  G06F40/20

CPC classification number: G06F30/31 ,  G06F30/39 ,  G06F40/20

Abstract: Embodiments include herein are directed towards a system and method for intelligent intent recognition based electronic design. Embodiments may include receiving, using a processor, a natural language input from a user at an intent recognition model. Embodiments may also include performing intent recognition on the natural language input at the intent recognition model and providing an output from the intent recognition model to a command generator. Embodiments may further include generating a command based upon, at least in part, the output and executing the command at a target tool environment.

公开(公告)号：US10289788B1

公开(公告)日：2019-05-14

申请号：US14954033

申请日：2015-11-30

Applicant: Cadence Design Systems, Inc.

Inventor： Hitesh Mohan Kumar ,  Matthew Timothy Bromley ,  Vikas Kohli ,  Sagar Kumar

IPC: G06F17/50 ,  G06F16/22 ,  G06F16/28

Abstract: The present disclosure relates to a computer-implemented method for electronic design automation. Embodiments may include storing one or more electronic circuit designs at an electronic circuit design database and receiving a user input associated with one of the electronic circuit designs. Embodiments may include scanning the one or more stored electronic circuit designs and generating a network including a relationship graph and a component map, based upon, at least in part, the scanning Embodiments may include generating at least one next neighbor component based upon, at least in part, the network and the received user input. Embodiments may include displaying one or more user-selectable options at a graphical user interface, wherein the user-selectable options include the at least one next neighbor component.

公开(公告)号：US10558774B1

公开(公告)日：2020-02-11

申请号：US15863557

申请日：2018-01-05

Applicant: Cadence Design Systems, Inc.

Inventor： Hitesh Mohan Kumar ,  Raghav Sharma

IPC: G06F17/50 ,  G06T7/143 ,  G06K9/32 ,  G06T7/11

Abstract: The present embodiments are generally directed to electronic circuit design and verification and more particularly to techniques for generating electronic design element symbols for electronic circuit design tool libraries and designs in any desired format. In embodiments, such electronic design element symbols can be generated from a datasheet or any other image using image processing, graphical shape and text recognition techniques. Embodiments use step by step processing to extract feature vectors from a symbol/design image, apply text and graphical shapes recognition using models, apply techniques for data association and write the final output for targeted systems. These and other embodiments can feed back the output data for further refinement of the recognition models.

公开(公告)号：US11270050B1

公开(公告)日：2022-03-08

申请号：US17232724

申请日：2021-04-16

Applicant: Cadence Design Systems, Inc.

Inventor： Hitesh Mohan Kumar ,  Anuj Jain ,  Sahil Vij ,  Abhimanyu Bhowmik ,  Rahul Kumar

IPC: G06F30/30 ,  G06F30/31 ,  G06F30/392 ,  G06F30/337 ,  G06F119/06 ,  G06F115/08 ,  G06F111/12 ,  G06F111/20 ,  G06F111/02

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include displaying, at a graphical user interface, at least a portion of the electronic design and receiving a selection of a subcircuit at a first position of the graphical user interface. In response to a user input, embodiments may include transitioning the subcircuit from the first position to a second position of the graphical user interface and determining one or more direct and indirect connections resulting from a potential placement at the second position. Embodiments may include determining an influence metric by applying an optimized connectivity rules definition upon the potential placement at the second position and the one or more direct and indirect connections. Embodiments may also include displaying feedback at the graphical user interface based upon, at least in part, the influence metric.

公开(公告)号：US09645715B1

公开(公告)日：2017-05-09

申请号：US14152197

申请日：2014-01-10

Applicant: Cadence Design Systems, Inc.

Inventor： Abha Jain ,  Hitesh Mohan Kumar ,  Parag Choudhary ,  Viren Agarwal

IPC: G06F3/048 ,  G06F3/0484

CPC classification number: G06F17/5068 ,  G06F17/5036 ,  G06F17/5045

Abstract: The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include receiving, using at least one processor, an electronic design and displaying, at a graphical user interface, at least a portion of the electronic design. Embodiments may also include allowing a user to select at least one design variable at the graphical user interface. Embodiments may also include simulating the electronic design, based upon, at least in part, the selected at least one design variable and in response to the simulation, automatically displaying an updated value at the graphical user interface.