公开(公告)号：US08527934B2

公开(公告)日：2013-09-03

申请号：US13692960

申请日：2012-12-03

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Theodore A. Paone ,  Gerard Tarroux ,  Jim Newton ,  Jean-Noel Pic

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5068 ,  G06F17/5072

Abstract: Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.

Abstract translation: 公开了一种用于实现电子设计的改进机制和方法。 根据一些方法，公开了一种用于实现电子设计的方法，机制和计算程序产品，其允许使用高级编辑特征对复杂对象进行可视编辑，其还提供编辑结果与可编程对象的参数值的自动对应 该设计。

公开(公告)号：US10783312B1

公开(公告)日：2020-09-22

申请号：US16157011

申请日：2018-10-10

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Jean Marie Gustave Ginetti ,  Gerard Tarroux ,  Jean-Noel Pic ,  Xavier Alasseur

IPC: G06F17/50 ,  G06F30/398 ,  G06F30/367 ,  G06F30/392 ,  G06F111/20

Abstract: Disclosed are methods, systems, and articles of manufacture for determining layout equivalence between a plurality of versions of a single layout of a multi-fabric electronic design. These techniques identify a first version and a second version of a layout of an electronic design that spans across multiple design fabrics. One or more collaborative comparator modules are executed to determine whether the first version is identical to or different from the second version of the layout. These techniques further modify the first version or the second version of the layout with discrepancy annotation.

公开(公告)号：US09761204B1

公开(公告)日：2017-09-12

申请号：US14501219

申请日：2014-09-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Arnold Ginetti ,  Jean-Noel Pic ,  Philippe Bourdon ,  Gerard Tarroux

IPC: G06T1/20 ,  G09G5/36 ,  G06T1/60 ,  G09G5/377

CPC classification number: G09G5/363 ,  G06T1/20 ,  G06T1/60 ,  G09G5/377 ,  G09G2340/10 ,  G09G2360/02

Abstract: A system and method are provided for accelerated graphic rendering a view of a design layout view represented by a plurality of graphic objects defined by respective geometry data therefor. A database stores the geometry data having location and geometric portions. A large object module actuates retrieval of the geometry data for each of the graphic objects within the view selectively classified to be a large object. A small object module actuates partial retrieval of the geometry data for each of the graphic objects within the view selectively classified to be a small object, the location portion being thereby retrieved exclusive of the geometric portion of the geometry data for each small object. A rendering control module generates a composite image of the design layout view for display, which includes a geometric reproduction of each large object and an abstracted representation of each small object within the view.

公开(公告)号：US09141746B1

公开(公告)日：2015-09-22

申请号：US14231578

申请日：2014-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Jean-Noel Pic ,  Stephane Berger

IPC: G06F17/50 ,  G06F3/0484

CPC classification number: G06F17/5068 ,  G06F17/5072

Abstract: A system and method for enabling the display and movement of a boundary box of an instance master inclusive of specific predetermined geometric figures, including master pins, master halo and master boundary edges, is provided. The system and method provides for improved utilization of computer resources and enables users of the present invention to be able to drag and use instance master in their designs more efficiently and rapidly.

Abstract translation: 提供了一种用于实现包括主引脚，主光晕和主边界边缘的特定预定几何图形的实例主体的边界框的显示和移动的系统和方法。 该系统和方法提供了改进的计算机资源的利用，并且使本发明的用户能够更有效和快速地在其设计中拖放和使用实例主设备。

公开(公告)号：US09092586B1

公开(公告)日：2015-07-28

申请号：US14292661

申请日：2014-05-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Arnold Jean-Marie Gustave Ginetti ,  Jean-Noel Pic ,  Manav Khanna ,  Reenee Tayal ,  Mayank Sharma ,  Gerard Tarroux

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F8/71

Abstract: A version management system for fluid guard ring (FGR) PCells uses one or more new version management parameters that are added to the FGR PCell definition to manage the source code versions for a PCell. The system saves instance layout information with a version management parameter that identifies the current PCell source code version for each FGR PCell instance. When evaluated using a newer version of the PCell source code, the instance layout information generated with a previous version of PCell source code can be retrieved. The retrieved layout information will be used during evaluation of the PCell to ensure the integrity of the PCell geometries that were previously verified. The saved layout information will be uniquely identifiable with a hash code of the name-value pairs for one or more parameters associated with the PCell instance.

Abstract translation: 流体保护环（FGR）的版本管理系统PCells使用一个或多个添加到FGR PCell定义的新版本管理参数来管理PCell的源代码版本。 系统使用版本管理参数保存实例布局信息，该参数标识每个FGR PCell实例的当前PCell源代码版本。 当使用较新版本的PCell源代码进行评估时，可以检索使用PCell源代码的先前版本生成的实例布局信息。 在PCell的评估期间将使用检索到的布局信息，以确保先前验证的PCell几何的完整性。 保存的布局信息将使用与PCell实例相关联的一个或多个参数的名称 - 值对的哈希码进行唯一标识。

公开(公告)号：US10331841B1

公开(公告)日：2019-06-25

申请号：US14997239

申请日：2016-01-15

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Jean-Noel Pic

IPC: G06F17/50

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing virtual prototyping for electronic designs. These techniques identify a plurality of leaf cells into a hierarchical physical design of an electronic design, generate the hierarchical physical design at least by performing hierarchical placement for the plurality of leaf cells based in part or in whole upon one or more factors, and revise the placed hierarchical physical design at least by performing hierarchical routing for the plurality of leaf cells on the hierarchical physical design. One aspect may further detach a virtual cell in the hierarchical physical design at least by grouping a first set of leaf cells and representing the first set of leaf cells with a first placeholder.

公开(公告)号：US09842183B1

公开(公告)日：2017-12-12

申请号：US14869505

申请日：2015-09-29

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Arnold Ginetti ,  Gerard Tarroux ,  Jean-Noel Pic ,  Olivier Arnaud ,  Devendra Deshpande

IPC: G06F17/50 ,  G06F17/24 ,  G06F3/0481 ,  G06F17/30 ,  G06F3/0484 ,  G06F7/00

CPC classification number: G06F17/5072 ,  G06F3/0481 ,  G06F3/04842 ,  G06F7/00 ,  G06F17/24 ,  G06F17/30312 ,  G06F17/30979 ,  G06F17/5022

Abstract: Methods and systems of an electronic circuit design system described herein provide a new layout editor tool to make edits in an electronic circuit layout. A plurality of partitions is created in the electronic circuit layout. The new layout editor tool enables multiple electronic circuit designers to edit a different partition of the plurality of partitions of the same electronic circuit layout at the same time and save the edited partition locally.

公开(公告)号：US09830417B1

公开(公告)日：2017-11-28

申请号：US15204776

申请日：2016-07-07

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Arnold Ginetti ,  Jean-Noel Pic ,  Alexander B Wong ,  Devendra Deshpande

IPC: G06F17/50 ,  G06F3/0481 ,  G06F17/30

CPC classification number: G06F17/5072 ,  G06F3/0481 ,  G06F17/30312 ,  G06F17/30345 ,  G06F17/30557

Abstract: An electronic circuit design system for generating a programmable set of figures of an electronic circuit layout is provided. The system includes a non-transitory machine-readable layout database storing an electronic circuit layout of an electronic circuit design. The system further includes a circuit designer interface for viewing representations of the electronic circuit layout on a display unit and receiving inputs by one or more electronic circuit designers. The system further includes a processor configured to generate a figure group in the electronic circuit layout of the electronic circuit design; generate one or more templates comprising one or more parameters and a programming language code; and generate a parameterized figure group by associating the one or more templates to the figure group.

公开(公告)号：US20130097572A1

公开(公告)日：2013-04-18

申请号：US13692960

申请日：2012-12-03

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Theodore A. Paone ,  Gerard Tarroux ,  Jim Newton ,  Jean-Noel Pic

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5068 ,  G06F17/5072

Abstract: Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.

Abstract translation: 公开了一种用于实现电子设计的改进机制和方法。 根据一些方法，公开了一种用于实现电子设计的方法，机制和计算程序产品，其允许使用高级编辑特征对复杂对象进行可视编辑，其还提供编辑结果与可编程对象的参数值的自动对应 该设计。