公开(公告)号：US10223484B1

公开(公告)日：2019-03-05

申请号：US14231497

申请日：2014-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Donald J. O'Riordan ,  Richard J. O'Donovan ,  Saibal Saha ,  Jushan Xie

IPC: G05B23/02 ,  G06F17/50

Abstract: A system, method, and computer program product for facilitating model binning in circuit simulators. Embodiments enable specification of models spanning binning dimensions, such as device width and length, in a model group via inheritable model bins. New simulator modeling syntax and semantics eliminate much of the redundancy and parsing overhead from model parameter specifications in foundry process design kits. Indirect and optional inheritance is also enabled, allowing for fine grain and coarse grain grids in the same model group.

公开(公告)号：US09411918B1

公开(公告)日：2016-08-09

申请号：US13950212

申请日：2013-07-24

Applicant: Cadence Design Systems, Inc.

Inventor： John O'Donovan ,  Jushan Xie ,  Saibal Saha

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5036

Abstract: A system, method, and computer program product for extending device model parameter specification flexibility when using a subcircuit wrapper. Embodiments facilitate device modeling by allowing a modeling engineer to eliminate the explicit specification of a large set of wrapped device instance parameters as parameters to the subcircuit wrapper itself. A circuit designer may now use the subcircuit wrapper to specify an instance of the subcircuit without having to explicitly provide values for all such parameters. The simulator program's built-in device model calculates its default parameter values, which are often the result of complex expressions involving the other parameters, resulting in more accurate simulations. Subcircuit wrappers no longer need to be explicitly regenerated when a new version of the wrapped device model becomes available for the simulator (e.g., one that supports additional instance parameters that were not present on the earlier version when the subcircuit wrapper was created).

Abstract translation: 一种系统，方法和计算机程序产品，用于在使用子电路包装器时扩展设备模型参数规范的灵活性。 实施例通过允许建模工程师消除作为子电路包装器本身的参数的大量包装设备实例参数的明确规定来实现设备建模。 电路设计者现在可以使用子电路封装来指定子电路的实例，而不必为所有这些参数明确地提供值。 模拟器程序的内置设备模型计算其默认参数值，这通常是涉及其他参数的复杂表达式的结果，导致更准确的模拟。 当新版本的包装设备模型变得可用于模拟器时（例如，当创建子电路包装器时，支持其它实例参数不在早期版本中）时，子电路包装器不再需要显式重新生成。

公开(公告)号：US08954908B1

公开(公告)日：2015-02-10

申请号：US13939117

申请日：2013-07-10

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Jushan Xie ,  Michael Tian ,  An-Chang Deng

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/10

Abstract: A system, method, and computer program product for automatically approximating conventional Monte Carlo statistical device model evaluation for circuit simulation with drastic speed improvements, while preserving significant accuracy. Embodiments enable quick inspection of the effects of process mismatch variations on single devices and even large circuits compared to standard computationally prohibitive Monte Carlo analysis. Statistical device model variation is calculated as if all such variation is due to changes in threshold voltage, even though other physical phenomena are known to contribute. Threshold voltage variation is modeled as a function of statistical variation, device size, and working bias condition. Circuit simulation is faster when the full internal device model parameter set is not rebuilt for every Monte Carlo analysis iteration. Embodiments are compatible with both conventional SPICE and newer Fast SPICE simulations. Circuit designers may capture design sensitivity to manufacture process changes more easily with simplified statistical models.

Abstract translation: 一种系统，方法和计算机程序产品，用于自动逼近传统的蒙特卡罗统计设备模型评估电路仿真，同时保持显着的精度。 与标准的计算禁止蒙特卡洛分析相比，实施例能够快速检查单个装置甚至大电路上的工艺不匹配变化的影响。 计算统计设备模型的变化，好像所有这些变化都是由于阈值电压的变化，即使其他物理现象已知有贡献。 阈值电压变化被建模为统计变化，器件尺寸和工作偏置条件的函数。 对于每个蒙特卡罗分析迭代，当不重建完整的内部设备模型参数集时，电路仿真更快。 实施例与传统的SPICE和更新的Fast SPICE仿真兼容。 电路设计人员可以通过简化的统计模型来捕获设计灵敏度，更容易地制造过程变化。