公开(公告)号：US09213787B1

公开(公告)日：2015-12-15

申请号：US14231506

申请日：2014-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Richard J. O'Donovan ,  Donald J. O'Riordan

IPC: G06F17/50

CPC classification number: G06F17/5009

Abstract: A system, method, and computer program product for improving circuit reliability via circuit schematic simulation. A circuit simulator may netlist and simulate a schematic with a reference stimulus and determine whether a circuit component is a candidate for stress analysis, and store candidate component circuit conditions. A stress test simulation may determine if candidate components are stressed by exposure to simulated conditions meeting a stress test criterion, and output information regarding stressed circuit components. Embodiments may simulate analog integrated circuitry, determine MOS component gate oxide layer area according to component length and width, and monitor conditions on components deemed most likely to be defective, including larger MOS components. A circuit simulator plug-in may avoid storing simulation output waveforms or performing layout based analysis. Embodiments may modify the netlist and/or the test stimulus to increase the percentage of stressed circuit components, including bypassing voltage regulators and adding test connections.

Abstract translation: 一种通过电路原理图模拟改善电路可靠性的系统，方法和计算机程序产品。 电路模拟器可以用参考刺激网表和模拟原理图，并确定电路组件是否是应力分析的候选者，并存储候选组件电路条件。 应力测试模拟可以通过暴露于满足压力测试标准的模拟条件来确定候选部件是否受到应力，并且输出关于应力电路部件的信息。 实施例可以模拟模拟集成电路，根据元件长度和宽度确定MOS元件栅极氧化物层面积，并且监视被认为最有可能是有缺陷的元件（包括较大的MOS元件）的条件。 电路模拟器插件可以避免存储模拟输出波形或执行基于布局的分析。 实施例可以修改网表和/或测试刺激，以增加应力电路组件的百分比，包括旁路电压调节器和添加测试连接。

公开(公告)号：US10395000B1

公开(公告)日：2019-08-27

申请号：US14973341

申请日：2015-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： John Yanjiang Shu ,  Wei Michael Tian ,  Richard J. O'Donovan

IPC: G06F17/50

Abstract: Various embodiments implement an electronic design with one or more electrical analyses or simulations. Pre-layout and/or post-layout design data of an electronic design or a portion thereof may be identified at a physical design implementation module. A first stage analysis may be performed on the electronic design or the portion thereof at least by computing electrical characteristics with a reduced representation in the electronic design or the portion thereof. Electrical behavior of the electronic design or the portion thereof may be generated at least by performing a second stage analysis on the electronic design or the portion thereof with one or more adjusted electrical characteristics. The electronic design or the portion thereof may then be implemented based in part or in whole upon the one or more electrical analyses or simulations.

公开(公告)号：US10853550B1

公开(公告)日：2020-12-01

申请号：US16027231

申请日：2018-07-03

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu ,  Richard J. O'Donovan ,  Michael Tian

IPC: G06F30/367 ,  G06F17/50 ,  G06F111/10 ,  G06F119/18

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

公开(公告)号：US10223484B1

公开(公告)日：2019-03-05

申请号：US14231497

申请日：2014-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Donald J. O'Riordan ,  Richard J. O'Donovan ,  Saibal Saha ,  Jushan Xie

IPC: G05B23/02 ,  G06F17/50

Abstract: A system, method, and computer program product for facilitating model binning in circuit simulators. Embodiments enable specification of models spanning binning dimensions, such as device width and length, in a model group via inheritable model bins. New simulator modeling syntax and semantics eliminate much of the redundancy and parsing overhead from model parameter specifications in foundry process design kits. Indirect and optional inheritance is also enabled, allowing for fine grain and coarse grain grids in the same model group.

公开(公告)号：US10909293B1

公开(公告)日：2021-02-02

申请号：US16655570

申请日：2019-10-17

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu ,  Richard J. O'Donovan ,  Michael Tian

IPC: G06F30/367 ,  G06F119/18 ,  G06F111/10

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

公开(公告)号：US10216887B1

公开(公告)日：2019-02-26

申请号：US14974570

申请日：2015-12-18

Applicant: Cadence Design Systems, Inc.

Inventor： John Yanjiang Shu ,  Wei Michael Tian ,  Richard J. O'Donovan

IPC: G06F17/50

Abstract: Various embodiments implement an electronic design with power gate analyses using time varying resistors. Design data of an electronic design or a portion thereof may be identified at an electronic design implementation module. First stage electrical characteristics may be generated at least by performing a first stage electrical analysis on a reduced representation of the electronic design or the portion thereof. Second stage electrical characteristics may further be generated at least by performing a second stage electrical analysis on a parasitic injected representation of the electronic design or the portion thereof with a time-varying model for the power gate. The electronic design or the portion thereof may then be further implemented based in part or in whole upon the one or more electrical analyses or simulations.

公开(公告)号：US09038008B1

公开(公告)日：2015-05-19

申请号：US14231410

申请日：2014-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Donald J. O'Riordan ,  Jaideep Mukherjee ,  Richard J. O'Donovan

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5036 ,  G06F2217/14

Abstract: A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist. Vunits may also contain instance statements to monitor or process signals, such as those needed by assertions.

Abstract translation: 一种用于包含用于电路仿真的模拟验证IP的系统，方法和计算机程序产品。 实施例引入模拟验证单元（“vunits”）以及对应的模拟验证文件以包含它们。 Vunits允许通过文本文件进行电路设计验证要求规范。 不需要编辑包含设计IP的网表文件来实现静态和动态电路检查，PSL断言，时钟语句或遗留断言。 Vunits参考顶级电路或子电路（按名称或特定实例），并且模拟器在电路层级扩展期间自动绑定vunit内容。 Vunits可能会重新用于其他设计单元，并且可以通过基于文本的设计工具轻松处理。 可以通过控制网表文件，命令行参数中的vunit_include语句或直接将一个单元块放入网表中来提供Vunits。 Vunits还可以包含用于监视或处理信号的实例语句，例如断言所需的信号。