公开(公告)号：US08954908B1

公开(公告)日：2015-02-10

申请号：US13939117

申请日：2013-07-10

Applicant: Cadence Design Systems, Inc.

Inventor： Hongzhou Liu ,  Jushan Xie ,  Michael Tian ,  An-Chang Deng

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/10

Abstract: A system, method, and computer program product for automatically approximating conventional Monte Carlo statistical device model evaluation for circuit simulation with drastic speed improvements, while preserving significant accuracy. Embodiments enable quick inspection of the effects of process mismatch variations on single devices and even large circuits compared to standard computationally prohibitive Monte Carlo analysis. Statistical device model variation is calculated as if all such variation is due to changes in threshold voltage, even though other physical phenomena are known to contribute. Threshold voltage variation is modeled as a function of statistical variation, device size, and working bias condition. Circuit simulation is faster when the full internal device model parameter set is not rebuilt for every Monte Carlo analysis iteration. Embodiments are compatible with both conventional SPICE and newer Fast SPICE simulations. Circuit designers may capture design sensitivity to manufacture process changes more easily with simplified statistical models.

Abstract translation: 一种系统，方法和计算机程序产品，用于自动逼近传统的蒙特卡罗统计设备模型评估电路仿真，同时保持显着的精度。 与标准的计算禁止蒙特卡洛分析相比，实施例能够快速检查单个装置甚至大电路上的工艺不匹配变化的影响。 计算统计设备模型的变化，好像所有这些变化都是由于阈值电压的变化，即使其他物理现象已知有贡献。 阈值电压变化被建模为统计变化，器件尺寸和工作偏置条件的函数。 对于每个蒙特卡罗分析迭代，当不重建完整的内部设备模型参数集时，电路仿真更快。 实施例与传统的SPICE和更新的Fast SPICE仿真兼容。 电路设计人员可以通过简化的统计模型来捕获设计灵敏度，更容易地制造过程变化。

公开(公告)号：US10909293B1

公开(公告)日：2021-02-02

申请号：US16655570

申请日：2019-10-17

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu ,  Richard J. O'Donovan ,  Michael Tian

IPC: G06F30/367 ,  G06F119/18 ,  G06F111/10

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

公开(公告)号：US10853550B1

公开(公告)日：2020-12-01

申请号：US16027231

申请日：2018-07-03

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Hongzhou Liu ,  Richard J. O'Donovan ,  Michael Tian

IPC: G06F30/367 ,  G06F17/50 ,  G06F111/10 ,  G06F119/18

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.