公开(公告)号：US09129078B1

公开(公告)日：2015-09-08

申请号：US14067720

申请日：2013-10-30

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Vinod Kariat ,  King Ho Tam

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5036 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/82 ,  G06F2217/84

Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.

Abstract translation: 公开了在存在噪声的情况下用于集成电路设计的静态时序分析的系统，装置和方法。 集成电路设计可以被划分成多个电路级。 包括定时弧的定时图被构造成表示集成电路设计的电路阶段中的时序延迟。 可以形成每个电路级的模型，其包括耦合在一起的受害者驱动器，攻击者驱动器，受害者接收器以及受害者网络和侵略者网络的模型。 对于定时图中的每个定时电弧，可以为每个电路级中的定时弧计算全定时延迟。

公开(公告)号：US08966421B1

公开(公告)日：2015-02-24

申请号：US14023450

申请日：2013-09-10

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kariat ,  Igor Keller ,  Joel R. Phillips ,  King Ho Tam

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F2217/84

Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

Abstract translation: 在本发明的一个实施例中，公开了一种多CCC电流源模型来执行集成电路设计的统计时序分析。 多CCC电流源模型包括电压波形传递函数，电压相关电流源和输出电容器。 电压波形传递函数接收输入电压波形并将其转换为中间电压波形。 电压相关电流源响应于中间电压波形产生输出电流。 输出电容器并联到与电压相关的电流源，以产生用于计算定时延迟的输出电压波形。