公开(公告)号：US10551435B1

公开(公告)日：2020-02-04

申请号：US15163351

申请日：2016-05-24

Applicant: Cadence Design Systems, Inc.

Inventor： Nitin Parimi ,  Krishna Vijaya Chakravadhanula ,  Patrick Wayne Gallagher ,  Vivek Chickermane ,  Brian Edward Foutz

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3183 ,  H03K3/012 ,  G01R31/3185 ,  H03K19/096 ,  G01R31/3187 ,  G11C16/32

Abstract: Systems and methods disclosed herein provide for an integrated circuit partitioned into a plurality of regions of a two-dimensional grid, wherein each region of the grid corresponds to similarly located scan flops. The systems and methods also provide for enabling clock gates to scan flops in some regions of the integrated circuit and disabling clock gates to other regions in order to better manage power dissipation during ATPG. Specifically, toggle disabling templates are applied during ATPG in order to enable clock gates in certain regions of the two-dimensional grid.

公开(公告)号：US10541043B1

公开(公告)日：2020-01-21

申请号：US15421158

申请日：2017-01-31

Applicant: Cadence Design Systems, Inc.

Inventor： Carl Alexander Wisnesky, II ,  Patrick Wayne Gallagher ,  Steven Lee Gregor ,  Norman Robert Card

IPC: G11C29/44 ,  G11C29/12 ,  G06F11/25

Abstract: Embodiments relate generally to a scalable, modularized mechanism which allows for storing programmable data streams on chip and provides repeatable on-demand issuances of data streams to one or more targeted instruments. In some embodiments, multiple data streams are grouped into data stream schedules to perform a series of programmable operations on demand. In these and other embodiments, data stream schedules can be reused and further grouped into data stream plans that can be executed in any order upon request or are hard-coded in a specific order.

公开(公告)号：US10060976B1

公开(公告)日：2018-08-28

申请号：US15151263

申请日：2016-05-10

Applicant: Cadence Design Systems, Inc.

Inventor： Sharjinder Singh ,  Sameer Chakravarthy Chillarige ,  Robert Jordan Asher ,  Sonam Kathpalia ,  Patrick Wayne Gallagher ,  Joseph Michael Swenton

IPC: G01R31/3173 ,  G01R31/317 ,  G01R31/3177 ,  G01R31/327

CPC classification number: G01R31/31703 ,  G01R31/31704 ,  G01R31/3177 ,  G01R31/318364 ,  G01R31/318371

Abstract: Systems and methods disclosed herein provide for automatically diagnosing mis-compares detected during simulation of Automatic Test Pattern Generation (“ATPG”) generated test patterns. Embodiments of the systems and methods provide for determining the origin of a mis-compare based on an analysis of the generated test patterns with a structural simulator and a behavioral simulator.