公开(公告)号：US11354477B1

公开(公告)日：2022-06-07

申请号：US17143371

申请日：2021-01-25

Applicant: Cadence Design Systems, Inc.

Inventor： Jasleen Kaur Ahuja ,  Taranjit Singh Kukal ,  Vikrant Khanna ,  Nikhil Gupta ,  Rohit Shukla ,  Kunal Gupta ,  Charu Kapoor

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/3953 ,  H01F27/06

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a printed circuit board schematic and one or more electronic circuits. Embodiments may further include automatically generating, one or more circuit templates based upon, at least in part, the printed circuit board schematic and one or more electronic circuits. The one or more circuit templates may be stored at an electronic design database. Embodiments may also include receiving a current printed circuit board schematic and automatically determining whether a subcircuit of the current printed circuit board schematic is an exact or approximate match with the one or more circuit templates.

公开(公告)号：US10997332B1

公开(公告)日：2021-05-04

申请号：US16583803

申请日：2019-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Siddharth Mohan ,  Vikrant Khanna ,  Kunal Gupta ,  Jasleen Kaur Ahuja ,  Nikhil Gupta

IPC: G06F30/30 ,  G06F30/31 ,  G06F30/367 ,  G06F30/33 ,  G06F30/3308 ,  G06F30/392 ,  G06F30/398 ,  G06F119/02 ,  G06F115/12 ,  G06F111/12

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and splitting, using the at least one processor, the electronic design schematic into a plurality of subcircuits. Embodiments may further include independently simulating each of the plurality of subcircuits to generate simulation results and analyzing the simulation results to determine over-stress associated with the plurality of subcircuits.