公开(公告)号：US09760666B1

公开(公告)日：2017-09-12

申请号：US15169239

申请日：2016-05-31

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Shilpa Gandotra ,  Aditya Chandra ,  Gunjan Goel ,  Inderpal Singh ,  Nikhil Gupta ,  Ishani Jain

IPC: G06F17/50 ,  H05K3/00

CPC classification number: G06F17/5045 ,  G06F2217/74

Abstract: A planned schematic for an electronic system is hierarchically divided into base-level schematic blocks which may be designed individually. In accordance with a plurality of sets of design requirements, variant overlays are designed for each base-level schematic block, each overlay including variant parameter values which may replace corresponding parameter values of the schematic blocks. The schematic blocks are integrated to generate a system-level schematic, and the variant overlays for a given set of design requirements are merged to generate a system variant overlay. Parameter values of the system variant overlay may then replace corresponding parameter values of the system-level schematic to generate a variant schematic for the given set of design requirements. Using this system and methodology, variant designs may be collaboratively generated by multiple designers each with expertise in particular schematic blocks and/or variant requirements, and may be shared either at the system level or at lower levels.

公开(公告)号：US10997332B1

公开(公告)日：2021-05-04

申请号：US16583803

申请日：2019-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Siddharth Mohan ,  Vikrant Khanna ,  Kunal Gupta ,  Jasleen Kaur Ahuja ,  Nikhil Gupta

IPC: G06F30/30 ,  G06F30/31 ,  G06F30/367 ,  G06F30/33 ,  G06F30/3308 ,  G06F30/392 ,  G06F30/398 ,  G06F119/02 ,  G06F115/12 ,  G06F111/12

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and splitting, using the at least one processor, the electronic design schematic into a plurality of subcircuits. Embodiments may further include independently simulating each of the plurality of subcircuits to generate simulation results and analyzing the simulation results to determine over-stress associated with the plurality of subcircuits.

公开(公告)号：US11354477B1

公开(公告)日：2022-06-07

申请号：US17143371

申请日：2021-01-25

Applicant: Cadence Design Systems, Inc.

Inventor： Jasleen Kaur Ahuja ,  Taranjit Singh Kukal ,  Vikrant Khanna ,  Nikhil Gupta ,  Rohit Shukla ,  Kunal Gupta ,  Charu Kapoor

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/3953 ,  H01F27/06

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a printed circuit board schematic and one or more electronic circuits. Embodiments may further include automatically generating, one or more circuit templates based upon, at least in part, the printed circuit board schematic and one or more electronic circuits. The one or more circuit templates may be stored at an electronic design database. Embodiments may also include receiving a current printed circuit board schematic and automatically determining whether a subcircuit of the current printed circuit board schematic is an exact or approximate match with the one or more circuit templates.

公开(公告)号：US10467370B1

公开(公告)日：2019-11-05

申请号：US15721851

申请日：2017-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Arnold Jean Marie Gustave Ginetti ,  Preeti Chauhan ,  Nikhil Gupta ,  Vikas Aggarwal ,  Vikrant Khanna

IPC: G06F17/50 ,  H05K3/00

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing a schematic circuit design component as a transmission line model in a schematic driven extracted view for an electronic design. These techniques identify a schematic circuit component design form a schematic design of an electronic design and identify or determine layout device information of a layout circuit component design corresponding to the schematic circuit component design. An extracted view may be generated or identified for the electronic design at least by using a transmission line model based in part or in whole upon connectivity information or a hierarchical structure of the electronic design. The electronic design may then be modified or updated based in part or in whole upon results of performing one or more analyses on the extracted view with the transmission line model.

公开(公告)号：US09934354B1

公开(公告)日：2018-04-03

申请号：US15205593

申请日：2016-07-08

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Balvinder Singh ,  Steven R. Durrill ,  Arnold Ginetti ,  Vikrant Khanna ,  Abhishek Dabral ,  Madhur Sharma ,  Nikhil Gupta ,  Ritabrata Bhattacharya

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5077 ,  G06F2217/40 ,  G06F2217/74

Abstract: Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.