公开(公告)号：US09859904B1

公开(公告)日：2018-01-02

申请号：US15278521

申请日：2016-09-28

Applicant: Cadence Design Systems, Inc.

Inventor： Mark Alan Summers

IPC: H03K21/00 ,  H03L7/197 ,  H03L7/099 ,  H03L7/089

CPC classification number: H03L7/0802 ,  H03L7/1976

Abstract: Systems and methods disclosed herein provide for a fractional feedback divider with reduced jitter at the output without increasing the input clock frequency and with minimal power increase. Embodiments of the system provide for interpolating, with a multiplexer, different output clock signals depending on whether an extra half period of resolution from the input clock is needed for a certain output clock cycle.

公开(公告)号：US09762378B1

公开(公告)日：2017-09-12

申请号：US15195598

申请日：2016-06-28

Applicant: Cadence Design Systems, Inc.

Inventor： Mark Alan Summers

IPC: H04L7/00 ,  H04B10/61 ,  H04L27/14

CPC classification number: H04B10/6165 ,  H03L7/085

Abstract: A phase difference multiplier circuit is disclosed that includes first and second delay circuits to apply two different quantities of delay to first and second input signals. The first and second delay circuits may operate in a first mode where a first and smaller amount of delay is imparted to the respective input signals. The first and second input signals differ in phase, and a transition in the first signal will be followed by a similar transition in the second signal. Following the transition of the first signal reaching the input of the first delay circuit, the similar transition will reach the input of the second delay circuit. In response to the transition reaching the input of the second delay circuit, the first and second delay circuits are then operated to impart a second and larger amount of delay to the first and second signals. At the output of the first and second delay circuits, the duration of the difference in phase between the first and second signals is increased by a multiplication factor. Extending the duration in such a manner may, for example, make the initial difference in phase easier to measure.

公开(公告)号：US10153774B1

公开(公告)日：2018-12-11

申请号：US15418327

申请日：2017-01-27

Applicant: Cadence Design Systems, Inc.

Inventor： Scott David Huss ,  Mark Alan Summers

IPC: H03L7/06 ,  H03L7/093 ,  H03F3/45

Abstract: A phase locked loop (PLL) circuit and a method for providing a transconductance in the PLL involve forming an input voltage to an operational amplifier by a loop filter. A voltage output of the operational amplifier controls a plurality of current mirrors. A current is formed through a first one of the current mirrors as a function of the input voltage, a resistance of a resistor, and a reference voltage. The reference voltage is directly provided by, or derived from, a reference signal. A second voltage formed in the first current mirror is fed back to the operational amplifier to maintain the current through the first current mirror, which current is then mirrored into at least a second one of the current mirrors to form an output current proportional to a difference between the input voltage and the reference voltage.

公开(公告)号：US10133292B1

公开(公告)日：2018-11-20

申请号：US15191678

申请日：2016-06-24

Applicant: Cadence Design Systems, Inc.

Inventor： Mark Alan Summers ,  Scott David Huss

IPC: G05F3/26

Abstract: Systems disclosed herein provide for a low-noise current mirror operable under low power supply requirements. Embodiments of the systems provide for a low input current path and a high input current path, wherein the current in the low current input path sees a higher voltage and the current in the high input current path sees a lower voltage. Embodiments of the system also provide for a cascode transistor in the high input current path.