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    Continuous time linear receiver that minimizes intersymbol interference due to pre-cursor distortion
    1.
    发明授权
    Continuous time linear receiver that minimizes intersymbol interference due to pre-cursor distortion 有权

    公开(公告)号：US10367661B1

    公开(公告)日：2019-07-30

    申请号：US15376525

    申请日：2016-12-12

    Applicant: Cadence Design Systems, Inc.

    Inventor： Scott David Huss

    IPC: H04L25/03 ,  H04L1/00 ,  H04L12/26

    Abstract: A circuit and method for reducing intersymbol interference due to pre-cursor distortion. A first set of circuit elements located along a first circuit path of a receiver device process an analog input signal of the receiver to form an equalized representation of the input signal. A second set of circuit elements are located along a second circuit path that has lower latency than the first circuit path. The second set of circuit elements form a scaled signal as one of the following: a scaled representation of the input signal, an inverted scaled representation of the input signal, a scaled derivative of the input signal, and an inverted scaled derivative of the input signal. The scaled signal is combined with the equalized representation to cancel out a pre-cursor portion of the equalized representation.

    Method of adaptively controlling a low frequency equalizer
    2.
    发明授权
    Method of adaptively controlling a low frequency equalizer 有权

    公开(公告)号：US09998303B1

    公开(公告)日：2018-06-12

    申请号：US15380474

    申请日：2016-12-15

    Applicant: Cadence Design Systems, Inc.

    Inventor： Scott David Huss ,  Loren Blair Reiss

    IPC: H03H7/30 ,  H04L25/03 ,  H04B1/16

    CPC classification number: H04L25/03057 ,  H04B1/16

    Abstract: A circuit and method for adaptively controlling an equalizer circuit to reduce intersymbol interference at low frequencies relative to a transmit frequency of an input signal from a transmitter. The input signal is converted into a data signal by a receiver. At least one delayed data signal is formed by delaying the data signal by at least one unit interval (UI) beyond a length of a decision feedback equalizer (DFE) in the receiver. An error signal is formed by comparing the input signal to a threshold value. An error signal sample is correlated with at least one delayed data signal sample to determine whether to adjust a control coefficient of the equalizer. Thus the equalizer is controlled as if the DFE had at least one additional tap.

    Transmitter test with interpolation
    3.
    发明授权
    Transmitter test with interpolation 有权

    公开(公告)号：US11238204B1

    公开(公告)日：2022-02-01

    申请号：US17066284

    申请日：2020-10-08

    Applicant: Cadence Design Systems, Inc.

    Inventor： Scott David Huss ,  Loren B. Reiss ,  Fred Staples Stivers ,  Steven Martin Broome

    IPC: G06F30/30 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3187 ,  G06F30/333

    Abstract: Various embodiments provide for testing a transmitter with interpolation, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer over a plurality of different interpolation phase positions of a phase interpolator; and using a pattern checker to error check the sampled data over the plurality of different interpolation phase positions to determine whether the data transmission test passes.

    Data alignment in physical layer device
    5.
    发明授权
    Data alignment in physical layer device 有权

    公开(公告)号：US11190331B1

    公开(公告)日：2021-11-30

    申请号：US17124280

    申请日：2020-12-16

    Applicant: Cadence Design Systems, Inc.

    Inventor： Loren B. Reiss ,  Scott David Huss ,  Fred Staples Stivers ,  James Dennis Vandersand, Jr.

    IPC: H04L7/00

    Abstract: A physical layer (PHY) device comprises a phase interpolator to generate a set of sampler clocks. A sampler of the PHY device samples a calibration data pattern based on the set of sampler clocks. A data alignment system of the PHY device performs a coarse calibration and a fine calibration on the sampler clock signals. During the coarse calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on a first bit of the sampled data. During the fine calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on the first bit, a second bit, and a third bit in the sampled data.

    Transconductor circuit for a fourth order PLL
    6.
    发明授权
    Transconductor circuit for a fourth order PLL 有权

    公开(公告)号：US10153774B1

    公开(公告)日：2018-12-11

    申请号：US15418327

    申请日：2017-01-27

    Applicant: Cadence Design Systems, Inc.

    Inventor： Scott David Huss ,  Mark Alan Summers

    IPC: H03L7/06 ,  H03L7/093 ,  H03F3/45

    Abstract: A phase locked loop (PLL) circuit and a method for providing a transconductance in the PLL involve forming an input voltage to an operational amplifier by a loop filter. A voltage output of the operational amplifier controls a plurality of current mirrors. A current is formed through a first one of the current mirrors as a function of the input voltage, a resistance of a resistor, and a reference voltage. The reference voltage is directly provided by, or derived from, a reference signal. A second voltage formed in the first current mirror is fed back to the operational amplifier to maintain the current through the first current mirror, which current is then mirrored into at least a second one of the current mirrors to form an output current proportional to a difference between the input voltage and the reference voltage.

    Low supply current mirror
    7.
    发明授权
    Low supply current mirror 有权

    公开(公告)号：US10133292B1

    公开(公告)日：2018-11-20

    申请号：US15191678

    申请日：2016-06-24

    Applicant: Cadence Design Systems, Inc.

    Inventor： Mark Alan Summers ,  Scott David Huss

    IPC: G05F3/26

    Abstract: Systems disclosed herein provide for a low-noise current mirror operable under low power supply requirements. Embodiments of the systems provide for a low input current path and a high input current path, wherein the current in the low current input path sees a higher voltage and the current in the high input current path sees a lower voltage. Embodiments of the system also provide for a cascode transistor in the high input current path.

    Dual path level shifter to reduce duty cycle distortion
    8.
    发明授权
    Dual path level shifter to reduce duty cycle distortion 有权

    公开(公告)号：US11190189B1

    公开(公告)日：2021-11-30

    申请号：US17005099

    申请日：2020-08-27

    Applicant: Cadence Design Systems, Inc.

    Inventor： Scott David Huss

    IPC: H03K19/0175 ,  H03K5/156 ,  H03K3/037 ,  G06F1/04

    Abstract: A level shifter circuit comprises a first and second path connected in parallel. The first path comprises three inverters connected in series, and the first path generates a first intermediate clock signal based on an input clock signal. The first intermediate clock signal has a first duty cycle distortion. The second path also comprises three inverters connected in series and the second path generates a second intermediate clock signal based on the input clock signal. The second intermediate clock signal has a second duty cycle distortion. A level shifter output provides an output clock signal based on a combination of the first and second intermediate clock signals. The combination of the first and second intermediate clock signals results in an averaging of the first and second duty cycle distortions in the output clock signal.

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