公开(公告)号：US11892501B1

公开(公告)日：2024-02-06

申请号：US17865104

申请日：2022-07-14

Applicant: Cadence Design Systems, Inc.

Inventor： Arvind Chokhani ,  Joseph M. Swenton ,  Martin Amodeo

IPC: G01R31/28

CPC classification number: G01R31/287 ,  G01R31/2879 ,  G01R31/2882

Abstract: An integrated circuit (IC) test engine generates N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of an IC design. A diagnostics engine that receives test result data characterizing application of the N-cycle at-speed test patterns to a fabricated IC chip based on the IC design by an ATE, in which the test result data includes a set of miscompare values characterizing a difference between an expected result and a result measured by the ATE for a given N-cycle at-speed test pattern. The diagnostics engine employs a fault simulator to fault-simulate the N-cycle at-speed test patterns against a fault model that includes a first set of transition faults and/or defects and fault-simulate a subset of the N-cycle at-speed test patterns against a fault model that includes multicycle transition faults and/or defects utilizing sim-shifting.