公开(公告)号：US11740284B1

公开(公告)日：2023-08-29

申请号：US17366227

申请日：2021-07-02

Applicant: Cadence Design Systems, Inc.

Inventor： Arvind Chokhani ,  Joseph Michael Swenton ,  Martin Thomas Amodeo

IPC: G01R31/3177 ,  G06F30/392 ,  G06F30/31

CPC classification number: G01R31/3177 ,  G06F30/392 ,  G06F30/31

Abstract: An integrated circuit (IC) test engine generates single cycle test patterns for testing for candidate faults and/or defects of a first set of static faults and/or defects of an IC design. A diagnostics engine receives single cycle test result data characterizing application of the single cycle test patterns to a fabricated IC chip based on the IC design and fault-simulates a subset of the single cycle test patterns against a fault model that includes multicycle faults and/or defects utilizing sim-shifting to diagnose a second set of static faults and/or defects in the fabricated IC chip that are only detectable with multicycle test patterns. The diagnostics engine further scores candidate faults and/or defects in the first set of static faults and/or defects and the second set of static faults and/or defects for applicable test patterns to determine a most likely fault and/or defect present in the fabricated IC chip.

公开(公告)号：US11893336B1

公开(公告)日：2024-02-06

申请号：US17499414

申请日：2021-10-12

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Arvind Chokhani ,  Joseph Michael Swenton ,  Martin Thomas Amodeo

IPC: G06F30/398 ,  G06F119/18 ,  G06F119/12

CPC classification number: G06F30/398 ,  G06F2119/12 ,  G06F2119/18

Abstract: An IC test engine generates a plurality of two-cycle delay test patterns that target a first set of multicycle faults and/or defects of a fabricated IC chip based on an IC design. Each two-cycle delay test pattern includes a scan-in shift window operating at a test clock frequency, and a capture window with a launch cycle and a capture cycle operating at a functional clock frequency. The IC test engine fault simulates the plurality of two-cycle delay test patterns against a second set of multicycle faults and/or defects in the IC design utilizing sim-shifting, such that a state of the IC design after at least a last two shift clock cycles of a scan-in shift in window of each two-cycle delay test pattern of the plurality of two-cycle delay test patterns are fault simulated to provide two fault initialization cycles for detection of a multicycle delay fault and/or defect.

公开(公告)号：US11579194B1

公开(公告)日：2023-02-14

申请号：US17342764

申请日：2021-06-09

Applicant: Cadence Design Systems, Inc.

Inventor： Arvind Chokhani ,  Joseph Michael Swenton ,  Martin Thomas Amodeo

IPC: G01R31/28 ,  G06F11/00 ,  G01R31/3183 ,  G01R31/3185

Abstract: An integrated circuit (IC) test engine can generate a plurality of single cycle test patterns that target a plurality of static single cycle defects of a fabricated IC chip based on an IC design. The IC test engine can also fault simulate the plurality of single cycle test patterns against a plurality of multicycle defects in the IC design, wherein a given single cycle test pattern of the plurality of single cycle test patterns is sim-shifted to enable detection of a given multicycle fault and/or defect of the plurality of multicycle faults and/or defects.