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    Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs
    1.
    发明授权
    Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs 有权
    电子电路设计同步分层实施的方法，系统和制造

    公开(公告)号：US08769455B1

    公开(公告)日：2014-07-01

    申请号：US13719058

    申请日：2012-12-18

    Applicant: Cadence Design Systems, Inc.

    Inventor： Sushobhit Singh ,  Amit Kumar ,  Oleg Levitsky

    IPC: G06F17/50 ,  G06F9/455

    CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F2217/84

    Abstract: Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet closure requirements such that a total number of iterations of the reassembly process, which integrates lower level blocks into top level design, may be reduced or completely eliminated. The design attribute(s) or the connectivity model(s) or information is updated upon the identification of changes to provide the latest information or data for properly closing a design.

    Abstract translation: 各种实施例使用连通性信息或模型，设计属性和系统智能层，以使较低级别的较低块知道在相同或不同级别的其他块中进行的改变，以在不同级别实现设计 同步地 执行预算设计以将预算分配到设计中的各个块。 可以从一个或多个块借用各种预算并借出块，以便该块满足关闭要求，使得可以减少将较低级别块集成到顶级设计中的重组过程的迭代次数 或完全消除。 设计属性或连接模型或信息将在识别更改时更新，以提供正确关闭设计的最新信息或数据。

    Systems and methods for arc-based debugging in an electronic design
    5.
    发明授权
    Systems and methods for arc-based debugging in an electronic design 有权

    公开(公告)号：US10733346B1

    公开(公告)日：2020-08-04

    申请号：US16218198

    申请日：2018-12-12

    Applicant: Cadence Design Systems, Inc.

    Inventor： Sushobhit Singh

    IPC: G06F30/3323 ,  G06F30/327 ,  G06F119/12

    Abstract: The present disclosure relates to a system for performing static timing analysis in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design at a debugging platform without performing a model extraction phase and mapping one or more extracted timing models (“ETM”) to one or more netlist objects associated with the electronic design. Embodiments may further include receiving, at the debugging platform, at least one timing arc specified by a source pin and a sink pin, wherein the at least one timing arc is associated with the electronic design. Embodiments may also include generating a worst timing path based upon, at least in part, the received at least one timing arc. Embodiments may further include generating characterization information for the at least one timing arc based upon, at least in part, one or more user-specified boundary conditions.

    Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs
    6.
    发明授权
    Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs 有权
    电子电路设计同步分层实施的方法，系统和制造

    公开(公告)号：US09053270B1

    公开(公告)日：2015-06-09

    申请号：US14298848

    申请日：2014-06-06

    Applicant: Cadence Design Systems, Inc.

    Inventor： Sushobhit Singh ,  Amit Kumar ,  Oleg Levitsky

    IPC: G06F17/50 ,  G06F9/455

    CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F2217/84

    Abstract: Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet closure requirements such that a total number of iterations of the reassembly process, which integrates lower level blocks into top level design, may be reduced or completely eliminated. The design attribute(s) or the connectivity model(s) or information is updated upon the identification of changes to provide the latest information or data for properly closing a design.

    Abstract translation: 各种实施例使用连通性信息或模型，设计属性和系统智能层，以使较低级别的较低块知道在相同或不同级别的其他块中进行的改变，以在不同级别实现设计 同步地 执行预算设计以将预算分配到设计中的各个块。 可以从一个或多个块借用各种预算并借出块，以便该块满足关闭要求，使得可以减少将较低级别块集成到顶级设计中的重组过程的迭代次数 或完全消除。 设计属性或连接模型或信息将在识别更改时更新，以提供正确关闭设计的最新信息或数据。

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