公开(公告)号：US10133841B1

公开(公告)日：2018-11-20

申请号：US15282792

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Chayan Majumder ,  Arnold Ginetti ,  Chandra Prakash Manglani ,  Amit Kumar

IPC: G06F17/50

Abstract: Disclosed are techniques for implementing three-dimensional or multi-layer integrated circuit designs. These techniques identify an electronic design and a plurality of inputs for implementing connectivity for the electronic design. Net distribution results may be generated at least by performing one or more net distribution analyzes. A bump in a bump array may then be assigned to a net that connects a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.

公开(公告)号：US09053270B1

公开(公告)日：2015-06-09

申请号：US14298848

申请日：2014-06-06

Applicant: Cadence Design Systems, Inc.

Inventor： Sushobhit Singh ,  Amit Kumar ,  Oleg Levitsky

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F2217/84

Abstract: Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet closure requirements such that a total number of iterations of the reassembly process, which integrates lower level blocks into top level design, may be reduced or completely eliminated. The design attribute(s) or the connectivity model(s) or information is updated upon the identification of changes to provide the latest information or data for properly closing a design.

Abstract translation: 各种实施例使用连通性信息或模型，设计属性和系统智能层，以使较低级别的较低块知道在相同或不同级别的其他块中进行的改变，以在不同级别实现设计 同步地 执行预算设计以将预算分配到设计中的各个块。 可以从一个或多个块借用各种预算并借出块，以便该块满足关闭要求，使得可以减少将较低级别块集成到顶级设计中的重组过程的迭代次数 或完全消除。 设计属性或连接模型或信息将在识别更改时更新，以提供正确关闭设计的最新信息或数据。

公开(公告)号：US08769455B1

公开(公告)日：2014-07-01

申请号：US13719058

申请日：2012-12-18

Applicant: Cadence Design Systems, Inc.

Inventor： Sushobhit Singh ,  Amit Kumar ,  Oleg Levitsky

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F2217/84

Abstract: Various embodiments use connectivity information or model(s), design attribute(s), and system intelligence layer(s) to make lower blocks at lower levels aware of changes made in other blocks at same or different levels to implement the design at different levels synchronously. Budgeting is performed for the design to distribute budgets to respective blocks in the design. The various budgets may be borrowed from one or more blocks and lent to a block in order for this block to meet closure requirements such that a total number of iterations of the reassembly process, which integrates lower level blocks into top level design, may be reduced or completely eliminated. The design attribute(s) or the connectivity model(s) or information is updated upon the identification of changes to provide the latest information or data for properly closing a design.

Abstract translation: 各种实施例使用连通性信息或模型，设计属性和系统智能层，以使较低级别的较低块知道在相同或不同级别的其他块中进行的改变，以在不同级别实现设计 同步地 执行预算设计以将预算分配到设计中的各个块。 可以从一个或多个块借用各种预算并借出块，以便该块满足关闭要求，使得可以减少将较低级别块集成到顶级设计中的重组过程的迭代次数 或完全消除。 设计属性或连接模型或信息将在识别更改时更新，以提供正确关闭设计的最新信息或数据。