公开(公告)号：US09798848B1

公开(公告)日：2017-10-24

申请号：US14475469

申请日：2014-09-02

Applicant: Cadence Design Systems, inc.

Inventor： Kumar Chidhambara Keshavan ,  Ambrish Kant Varma ,  Taranjit Singh Kukal ,  Rameet Pal ,  Bradford Griffin ,  Kenneth Robert Willis ,  Hui Qi ,  Xuegang Zeng

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations. Some other methods and systems are directed at performing channel analyses for a communication interface of an electronic system by concurrently applying stimuli to corresponding transmitters of a communication interface, characterizing the communication interface to perform a single simulation on the communication interface with the stimulus to determine responses at receivers of the communication interface, and determining waveform responses of the communication interface by performing operations on the responses and an input signal to the communication interface.

公开(公告)号：US10726188B1

公开(公告)日：2020-07-28

申请号：US15721278

申请日：2017-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Kumar Chidhambara Keshavan ,  Ambrish Kant Varma ,  Taranjit Singh Kukal ,  Rameet Pal ,  Bradford Griffin ,  Kenneth Robert Willis ,  Hui Qi ,  Xuegang Zeng

IPC: G06F30/00 ,  G06F30/398

Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations. Some other methods and systems are directed at performing channel analyses for a communication interface of an electronic system by concurrently applying stimuli to corresponding transmitters of a communication interface, characterizing the communication interface to perform a single simulation on the communication interface with the stimulus to determine responses at receivers of the communication interface, and determining waveform responses of the communication interface by performing operations on the responses and an input signal to the communication interface.

公开(公告)号：US10528688B1

公开(公告)日：2020-01-07

申请号：US15845322

申请日：2017-12-18

Applicant: Cadence Design Systems, Inc.

Inventor： Rameet Pal ,  Taranjit Singh Kukal ,  Rajesh Prasad Singh

IPC: G06F17/50 ,  G06T11/60 ,  G06F3/0484

Abstract: Embodiments include herein are directed towards a method for generating an input/output model from a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist. Embodiments may include receiving, using a processor, a SPICE netlist associated with an electronic design and selecting at least a portion of the SPICE netlist for analysis. Embodiments may further include reading the selected portion of the SPICE netlist and rendering a schematic symbol corresponding to the selected portion of the netlist. Embodiments may also include performing one or more operations associated with the schematic symbol and translating the one or more operations into simulation commands.