公开(公告)号：US10726188B1

公开(公告)日：2020-07-28

申请号：US15721278

申请日：2017-09-29

Applicant: Cadence Design Systems, Inc.

Inventor： Kumar Chidhambara Keshavan ,  Ambrish Kant Varma ,  Taranjit Singh Kukal ,  Rameet Pal ,  Bradford Griffin ,  Kenneth Robert Willis ,  Hui Qi ,  Xuegang Zeng

IPC: G06F30/00 ,  G06F30/398

Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations. Some other methods and systems are directed at performing channel analyses for a communication interface of an electronic system by concurrently applying stimuli to corresponding transmitters of a communication interface, characterizing the communication interface to perform a single simulation on the communication interface with the stimulus to determine responses at receivers of the communication interface, and determining waveform responses of the communication interface by performing operations on the responses and an input signal to the communication interface.

公开(公告)号：US10586011B1

公开(公告)日：2020-03-10

申请号：US15928627

申请日：2018-03-22

Applicant: Cadence Design Systems, Inc.

Inventor： Dennis Nagle ,  Amit Kumar Sharma ,  Delong Cai ,  Xuegang Zeng ,  Hui Qi

IPC: G06F17/50

Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include displaying, at a graphical user interface, an electronic circuit design topology environment and allowing a user to select, create, or modify an entirely single pin topology, an entirely multi-pin topology, or a combination of a single pin topology and a multi-pin topology for one or more portions of the electronic circuit design topology environment. Embodiments may also include receiving a selection of a designated portion of the electronic circuit design topology environment and generating, at the graphical user interface, a first, pin-adjustable symbol in accordance with the selected topology at the designated portion.

公开(公告)号：US09798848B1

公开(公告)日：2017-10-24

申请号：US14475469

申请日：2014-09-02

Applicant: Cadence Design Systems, inc.

Inventor： Kumar Chidhambara Keshavan ,  Ambrish Kant Varma ,  Taranjit Singh Kukal ,  Rameet Pal ,  Bradford Griffin ,  Kenneth Robert Willis ,  Hui Qi ,  Xuegang Zeng

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations. Some other methods and systems are directed at performing channel analyses for a communication interface of an electronic system by concurrently applying stimuli to corresponding transmitters of a communication interface, characterizing the communication interface to perform a single simulation on the communication interface with the stimulus to determine responses at receivers of the communication interface, and determining waveform responses of the communication interface by performing operations on the responses and an input signal to the communication interface.

公开(公告)号：US10380292B1

公开(公告)日：2019-08-13

申请号：US15094180

申请日：2016-04-08

Applicant: Cadence Design Systems, Inc.

Inventor： Kenneth Robert Willis ,  Jing Wang ,  Hui Qi ,  Xuegang Zeng ,  Zhen Mu

IPC: G06F17/00 ,  G01R13/00 ,  G01R31/00 ,  G06F17/50 ,  G01R31/28 ,  G01R31/3183 ,  G01R13/02 ,  G01R31/317

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and linking a printed circuit board (PCB) block to a physical layout associated with the electronic design. Embodiments may further include receiving, at a layout environment, at least one simulation parameter and performing, using a finite difference time domain (“FDTD”) simulator, a time-domain simulation, based upon, at least in part, the at least one simulation parameter.