公开(公告)号：US08880980B1

公开(公告)日：2014-11-04

申请号：US13686612

申请日：2012-11-27

Applicant: Cadence Design Systems, Inc.

Inventor： Anish Mathew ,  Sandeep Brahmadathan ,  Raveendra Pai G.

IPC: G11C29/00 ,  H03M13/05 ,  H03M13/15

CPC classification number: H03M13/15 ,  H03M13/13 ,  H03M13/152 ,  H03M13/27

Abstract: A system and method for expeditious transfer of data from a source device to a destination device in error corrected manner are provided. The system and method avoid the substantial delay in utilizing an intermediate buffer, determining error, and remediating the detected errors before even initializing a transfer of an input data from the source device to the destination device. Upon completion of error correction, only those portions corrected are retransmitted to the destination memory rather than the complete corrected input data. A by-pass section is provided for copying input data to the destination memory with at least a degree of parallelism with the error detection of the input data delivered to a parallel buffer coupled with the correction section by a splitter section.

Abstract translation: 提供了一种用于以错误校正的方式从源设备快速传送数据到目的地设备的系统和方法。 该系统和方法在初始化从源设备到目的设备的输入数据传输之前避免了利用中间缓冲器的实质性延迟，确定错误以及修复检测到的错误。 在完成纠错后，只有那些被校正的部分被重新发送到目的地存储器而不是完整的校正输入数据。 提供了一个旁路部分，用于将输入数据复制到目的地存储器，至少具有与通过分离器部分与校正部分耦合的并行缓冲器的输入数据的错误检测的并行度。