公开(公告)号：US09633159B1

公开(公告)日：2017-04-25

申请号：US14701193

申请日：2015-04-30

Applicant: Cadence Design Systems, Inc.

Inventor： Vipul Parikh ,  Lalit Bharat ,  Shagufta Siddique ,  Prashant Sethia ,  Naresh Kumar

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/84

Abstract: Disclosed is an improved approach to implement timing signoff and optimization. Integrated MMMC timing closure functionality is provided in a single software session. The system provides the capability to perform signoff analysis, debugging, ECO, and TSO optimization for a large number of MMMC views in single software session.