公开(公告)号：US10776547B1

公开(公告)日：2020-09-15

申请号：US16600927

申请日：2019-10-14

Applicant: Cadence Design Systems, Inc.

Inventor： Umesh Gupta ,  Naresh Kumar ,  Prashant Sethia ,  Ritika Govila ,  Jayant Sharma

IPC: G06F30/3312 ,  G06F16/901 ,  G06F119/12

Abstract: A static timing analysis system for finding timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use infinite-depth path-based analysis (IPBA) to achieve reduced pessimism as opposed to systems or methods employing only graph-based analysis (GBA), but with greatly reduced compute time requirements, or greater logic path coverage, versus systems or methods employing conventional or exhaustive path-based analysis. IPBA achieves the improved coverage or compute time results by slotting nodes of a circuit design graph into stages, propagating phases stage-by-stage for all paths in parallel, and merging phases wherever possible during the analysis.

公开(公告)号：US10289774B1

公开(公告)日：2019-05-14

申请号：US15474733

申请日：2017-03-30

Applicant: Cadence Design Systems, Inc.

Inventor： Pradeep Yadav ,  Ratnakar Goyal ,  Prashant Sethia ,  Manuj Verma

IPC: G06F17/50

Abstract: Various embodiments describe performing static timing analysis (STA) on a circuit design such that delay timing calculation results generated by an STA on the circuit design can be reused by subsequent STAs on the circuit design in place of performing a set of delay timing calculations on the circuit design.

公开(公告)号：US09589096B1

公开(公告)日：2017-03-07

申请号：US14716059

申请日：2015-05-19

Applicant: Cadence Design Systems, Inc.

Inventor： Umesh Gupta ,  Vishnu Kumar ,  Manish Bansal ,  Naresh Kumar ,  Manuj Verma ,  Prashant Sethia

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F2217/84

Abstract: Methods and systems provide setup and generation of SPICE results for a set of timing path(s) and integration of SPICE simulation with static timing analysis (STA) path-based results generation. In an embodiment, a method may select a candidate set of timing paths, perform path based analysis (PBA) on the selected paths, generate SPICE results for the selected paths, and render the PBA and SPICE results in an integrated user interface to facilitate sign off based on annotated constraints and correlation between STA results and SPICE results. Methods and systems of the present disclosure find application in, among other things, timing signoff in an electronic design and verification process.

Abstract translation: 方法和系统提供SPICE结果的设置和生成，用于一组定时路径以及SPICE仿真与静态时序分析（STA）基于路径的结果生成的集成。 在一个实施例中，方法可以选择候选的定时路径集合，在所选择的路径上执行基于路径的分析（PBA），为所选择的路径生成SPICE结果，并将PBA和SPICE结果呈现在集成的用户界面中以便于签名 基于注释约束和STA结果与SPICE结果之间的相关性。 本公开的方法和系统尤其涉及在电子设计和验证过程中的定时签发。

公开(公告)号：US09529962B1

公开(公告)日：2016-12-27

申请号：US14732160

申请日：2015-06-05

Applicant: Cadence Design Systems, Inc.

Inventor： Amit Dhuria ,  Pradeep Yadav ,  Manuj Verma ,  Naresh Kumar ,  Prashant Sethia

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/84

Abstract: The present disclosure relates to a computer-implemented method for use with an electronic design. Embodiments include identifying, using one or more processors, a plurality of sibling nets associated with the electronic design and determining if the plurality of sibling nets have a same input slew rate. If the plurality of sibling nets do not have a same input slew rate, embodiments also include determining a delay calculation (DC) for each of the plurality of sibling nets. If the plurality of sibling nets do have a same input slew rate, embodiments further include sharing a stored DC with the plurality of sibling nets.

Abstract translation: 本公开涉及一种用于电子设计的计算机实现的方法。 实施例包括使用一个或多个处理器识别与电子设计相关联的多个兄弟网，并确定多个兄弟网是否具有相同的输入转换速率。 如果多个兄弟网不具有相同的输入压摆率，则实施例还包括确定多个兄弟网中的每一个的延迟计算（DC）。 如果多个兄弟网确实具有相同的输入转换速率，则实施例还包括与多个兄弟网共享存储的DC。

公开(公告)号：US10114920B1

公开(公告)日：2018-10-30

申请号：US15197142

申请日：2016-06-29

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Umesh Gupta ,  Shashank Tripathi ,  Naresh Kumar ,  Arvind Nembili Veeravalli ,  Prashant Sethia ,  Ritika Govila

IPC: G06F17/50

Abstract: A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.

公开(公告)号：US08863052B1

公开(公告)日：2014-10-14

申请号：US13940576

申请日：2013-07-12

Applicant: Cadence Design Systems, Inc.

Inventor： Amit Dhuria ,  Naresh Kumar ,  Umesh Gupta ,  Pradeep Yadav ,  Prashant Sethia

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A system and method are provided for generating a structurally-aware timing model for operation of a predetermined circuit design. The timing model is generated to have a plurality of timing arcs representing timing characteristics of the circuit design. Additionally, terminal pairs of the circuit design are evaluated to determine characteristic structural weights for selected paths through the circuit design. The structurally-aware timing model may then be incorporated into a top-level hierarchical circuit design for timing analyses and pessimism removal to arrive at realistic timing characteristics. The structural weights are particularly helpful in an AOCV-type pessimism removal post-process.

Abstract translation: 提供了一种用于产生用于预定电路设计的操作的结构感知定时模型的系统和方法。 产生定时模型以具有表示电路设计的定时特性的多个定时弧。 另外，评估电路设计的端子对以确定通过电路设计的所选路径的特征结构权重。 结构感知定时模型然后可以被并入到顶级分级电路设计中，用于定时分析和悲观消除以达到实际的定时特性。 结构重量在AOCV型悲观消除后期处理中特别有用。

公开(公告)号：US09633159B1

公开(公告)日：2017-04-25

申请号：US14701193

申请日：2015-04-30

Applicant: Cadence Design Systems, Inc.

Inventor： Vipul Parikh ,  Lalit Bharat ,  Shagufta Siddique ,  Prashant Sethia ,  Naresh Kumar

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/84

Abstract: Disclosed is an improved approach to implement timing signoff and optimization. Integrated MMMC timing closure functionality is provided in a single software session. The system provides the capability to perform signoff analysis, debugging, ECO, and TSO optimization for a large number of MMMC views in single software session.

公开(公告)号：US09405882B1

公开(公告)日：2016-08-02

申请号：US14752206

申请日：2015-06-26

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Amit Dhuria ,  Naresh Kumar ,  Prashant Sethia ,  Jeannette Sutherland ,  Shashank Tripathi

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/84

Abstract: A static timing analysis method for input/output modes of an integrated circuit design, that includes loading the integrated circuit design described in a hardware description language into a memory. An active zone for static timing analysis is defined, which comprises logic and interconnect between an input/output port and a selected level of sequential logic elements upstream from an input port and downstream from an output port. A description of the active zone is generated using the hardware description language. Then a static timing analysis is performed on the logic of the active zone.

Abstract translation: 一种用于集成电路设计的输入/输出模式的静态时序分析方法，其包括以硬件描述语言描述的集成电路设计加载到存储器中。 定义了静态时序分析的活动区域，其包括输入/​​输出端口与输入端口上游和输出端口下游的顺序逻辑元件的选定级别之间的逻辑和互连。 使用硬件描述语言生成活动区域的描述。 然后对活动区域的逻辑执行静态时序分析。

公开(公告)号：US08788995B1

公开(公告)日：2014-07-22

申请号：US13842178

申请日：2013-03-15

Applicant: Cadence Design Systems, Inc.

Inventor： Naresh Kumar ,  Prashant Sethia ,  Amit Dhuria ,  Krishna Belkhale

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

Abstract: A system and method are provided for pessimism reduction of a timing database provided for optimization of a circuit design. Pessimism is reduced through generation of a hybrid graph-based static timing analysis (GBA) and path-based static timing analysis (PBA STA) database. PBA is selectively performed on the most critical GBA identified timing violations with the goal of reducing erroneous pessimism in operational timing characteristics passed on to the physical implementation corrective optimizer module to thereby reduce unnecessary fixing and transformations upon the circuit design to correspondingly reduce design time, temporary storage space, needed processing power for timing closure and to result in a finished operable and tangible circuit device with reduced area, power requirements, and decreased cost.

Abstract translation: 提供了一种系统和方法，用于减少为电路设计的优化提供的定时数据库的悲观情绪。 通过生成基于混合图的静态时序分析（GBA）和基于路径的静态时序分析（PBA STA）数据库来减少悲观。 选择性地对最关键的GBA识别的定时违规执行PBA，目的是减少传递到物理实现校正优化器模块的操作时序特性的错误悲观，从而减少电路设计上的不必要的固定和转换，从而相应地减少设计时间 存储空间，所需的处理能力用于定时关闭，并且导致完成的可操作和有形的电路装置，其面积减小，功率要求低，成本降低。