公开(公告)号：US09633159B1

公开(公告)日：2017-04-25

申请号：US14701193

申请日：2015-04-30

Applicant: Cadence Design Systems, Inc.

Inventor： Vipul Parikh ,  Lalit Bharat ,  Shagufta Siddique ,  Prashant Sethia ,  Naresh Kumar

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/84

Abstract: Disclosed is an improved approach to implement timing signoff and optimization. Integrated MMMC timing closure functionality is provided in a single software session. The system provides the capability to perform signoff analysis, debugging, ECO, and TSO optimization for a large number of MMMC views in single software session.

公开(公告)号：US11256837B1

公开(公告)日：2022-02-22

申请号：US16946666

申请日：2020-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Sourav Kumar Sircar ,  Marc Heyberger ,  Manish Garg ,  Akash Khandelwal ,  Chunlong Pan ,  Ruchir Agarwal ,  Anurag Saran ,  Lalit Bharat ,  Namrata M Sadhankar ,  Manish Bhatia ,  Renuka Deshpande

IPC: G06F30/33 ,  G06F30/327 ,  G06F119/06 ,  G06F119/12

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design with high-capacity design closure. A reduced netlist may be generated for an analysis view of an electronic design based at least in part upon logic of interest in the analysis view. A closure may be performed based at least in part upon a union netlist, wherein the union netlist is generated from the reduced netlist. The electronic design may then be implemented based at least in part upon a result of the closure task.