公开(公告)号：US11188696B1

公开(公告)日：2021-11-30

申请号：US16384815

申请日：2019-04-15

Applicant: Cadence Design Systems, Inc.

Inventor： Amit Dhuria ,  Sri Harsha Venkata Pothukuchi ,  Pradeep Yadav ,  Pawan Kulshreshtha ,  Igor Keller ,  Sharad Mehrotra ,  Jean Pierre Hiol ,  Krishna Prasad Belkhale

IPC: G06F30/30 ,  G06F30/3312 ,  G06F16/901 ,  G06F17/18

Abstract: An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.