公开(公告)号：US10289774B1

公开(公告)日：2019-05-14

申请号：US15474733

申请日：2017-03-30

Applicant: Cadence Design Systems, Inc.

Inventor： Pradeep Yadav ,  Ratnakar Goyal ,  Prashant Sethia ,  Manuj Verma

IPC: G06F17/50

Abstract: Various embodiments describe performing static timing analysis (STA) on a circuit design such that delay timing calculation results generated by an STA on the circuit design can be reused by subsequent STAs on the circuit design in place of performing a set of delay timing calculations on the circuit design.

公开(公告)号：US20240143877A1

公开(公告)日：2024-05-02

申请号：US17978002

申请日：2022-10-31

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Nikita Sergeev ,  Pradeep Yadav ,  Maksim Baranov

IPC: G06F30/3312 ,  G06F30/31

CPC classification number: G06F30/3312 ,  G06F30/31 ,  G06F2119/12

Abstract: Disclosed is an improved approach to implement sharing of delay calculations for replicated portions of a design, where input slews may be different between those replicated design portions. This allows the system to experience runtime improvements for timing analysis of electronic designs.

公开(公告)号：US09529962B1

公开(公告)日：2016-12-27

申请号：US14732160

申请日：2015-06-05

Applicant: Cadence Design Systems, Inc.

Inventor： Amit Dhuria ,  Pradeep Yadav ,  Manuj Verma ,  Naresh Kumar ,  Prashant Sethia

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/84

Abstract: The present disclosure relates to a computer-implemented method for use with an electronic design. Embodiments include identifying, using one or more processors, a plurality of sibling nets associated with the electronic design and determining if the plurality of sibling nets have a same input slew rate. If the plurality of sibling nets do not have a same input slew rate, embodiments also include determining a delay calculation (DC) for each of the plurality of sibling nets. If the plurality of sibling nets do have a same input slew rate, embodiments further include sharing a stored DC with the plurality of sibling nets.

Abstract translation: 本公开涉及一种用于电子设计的计算机实现的方法。 实施例包括使用一个或多个处理器识别与电子设计相关联的多个兄弟网，并确定多个兄弟网是否具有相同的输入转换速率。 如果多个兄弟网不具有相同的输入压摆率，则实施例还包括确定多个兄弟网中的每一个的延迟计算（DC）。 如果多个兄弟网确实具有相同的输入转换速率，则实施例还包括与多个兄弟网共享存储的DC。

公开(公告)号：US11188696B1

公开(公告)日：2021-11-30

申请号：US16384815

申请日：2019-04-15

Applicant: Cadence Design Systems, Inc.

Inventor： Amit Dhuria ,  Sri Harsha Venkata Pothukuchi ,  Pradeep Yadav ,  Pawan Kulshreshtha ,  Igor Keller ,  Sharad Mehrotra ,  Jean Pierre Hiol ,  Krishna Prasad Belkhale

IPC: G06F30/30 ,  G06F30/3312 ,  G06F16/901 ,  G06F17/18

Abstract: An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.

公开(公告)号：US09384310B1

公开(公告)日：2016-07-05

申请号：US14502611

申请日：2014-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Jijun Chen ,  Pradeep Yadav

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F2217/84

Abstract: A system and method for performing multi-mode multi-corner (MMMC) analysis such that multiple views or conditions can be analyzed together to improve runtime by taking advantage of common steps of analysis in different corners. Views are clustered based on their similarity to one another to take advantage of calculations and other tasks that may be shared between views during timing analysis. Then, during timing analysis, each net in the design is analyzed for each view.

Abstract translation: 一种用于执行多模式多角度（MMMC）分析的系统和方法，使得可以一起分析多个视图或条件以通过利用不同角落中的常见分析步骤来改善运行时间。 视图是基于彼此的相似性进行聚类，以利用在时序分析期间可以在视图之间共享的计算和其他任务。 然后，在时序分析期间，为每个视图分析设计中的每个网络。

公开(公告)号：US08863052B1

公开(公告)日：2014-10-14

申请号：US13940576

申请日：2013-07-12

Applicant: Cadence Design Systems, Inc.

Inventor： Amit Dhuria ,  Naresh Kumar ,  Umesh Gupta ,  Pradeep Yadav ,  Prashant Sethia

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A system and method are provided for generating a structurally-aware timing model for operation of a predetermined circuit design. The timing model is generated to have a plurality of timing arcs representing timing characteristics of the circuit design. Additionally, terminal pairs of the circuit design are evaluated to determine characteristic structural weights for selected paths through the circuit design. The structurally-aware timing model may then be incorporated into a top-level hierarchical circuit design for timing analyses and pessimism removal to arrive at realistic timing characteristics. The structural weights are particularly helpful in an AOCV-type pessimism removal post-process.

Abstract translation: 提供了一种用于产生用于预定电路设计的操作的结构感知定时模型的系统和方法。 产生定时模型以具有表示电路设计的定时特性的多个定时弧。 另外，评估电路设计的端子对以确定通过电路设计的所选路径的特征结构权重。 结构感知定时模型然后可以被并入到顶级分级电路设计中，用于定时分析和悲观消除以达到实际的定时特性。 结构重量在AOCV型悲观消除后期处理中特别有用。