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    System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit design
    1.
    发明授权
    System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit design 有权
    用于通用路径悲观的系统和方法减少时序分析，以指导电路设计的补救转换

    公开(公告)号：US08745561B1

    公开(公告)日：2014-06-03

    申请号：US13957373

    申请日：2013-08-01

    Applicant: Cadence Design Systems, Inc.

    Inventor： Vibhor Garg ,  Krishna Belkhale ,  Pawan Kulshreshtha ,  Hakan Yalcin

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G06F17/5031 ,  G06F2217/84

    Abstract: A system and method are provided for common path pessimism removal or reduction (CPPR) in a timing database provided to guide transformative physical optimization/correction of a circuit design for an IC product to remedy operational timing violations detected in the circuit design. Pessimism is reduced through generation of a common path pessimism removal (CPPR) tree structure of branching nodes, and operational timing characteristics of each node. The CPPR tree structure is used to avoid exponential phases propagating in an exploratory manner through the system design, as well as the resultant memory footprint thereof. Additionally, back-tracing node-by-node through the circuit design for each and every launch and capture flip flop pair end point through each possible path thereof is avoided.

    Abstract translation: 提供了一种系统和方法，用于在定时数据库中提供通用路径悲观消除或减少（CPPR），以指导用于IC产品的电路设计的变换物理优化/校正，以补救在电路设计中检测到的操作定时违规。 悲观主义通过生成分支节点的公共路径悲观消除（CPPR）树结构以及每个节点的运行时序特征来减少。 CPPR树结构用于避免通过系统设计以探索性方式传播的指数相位以及其产生的内存占用。 另外，避免了通过电路设计的每个启动和捕捉触发器对端点通过其每个可能的路径逐个跟踪节点。

    Timing context generation with multi-instance blocks for hierarchical analysis
    4.
    发明授权
    Timing context generation with multi-instance blocks for hierarchical analysis 有权

    公开(公告)号：US10169501B1

    公开(公告)日：2019-01-01

    申请号：US15182353

    申请日：2016-06-14

    Applicant: Cadence Design Systems, Inc.

    Inventor： Pawan Kulshreshtha ,  Amit Dhuria

    IPC: G06F17/50

    Abstract: Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

    Hierarchical timing analysis for multi-instance blocks
    5.
    发明授权
    Hierarchical timing analysis for multi-instance blocks 有权

    公开(公告)号：US10037394B1

    公开(公告)日：2018-07-31

    申请号：US15182338

    申请日：2016-06-14

    Applicant: Cadence Design Systems, Inc.

    Inventor： Pawan Kulshreshtha ,  Amit Dhuria

    IPC: G06F17/50

    CPC classification number: G06F17/5031 ,  G06F17/5045 ,  G06F2217/84

    Abstract: Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for all instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

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