公开(公告)号：US10234504B1

公开(公告)日：2019-03-19

申请号：US15452526

申请日：2017-03-07

Applicant: Cadence Design Systems, Inc.

Inventor： Subhasish Mukherjee ,  Jagjot Kaur ,  Vivek Chickermane ,  Susan Marie Genova

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

Abstract: According to certain aspects, the present embodiments relate to optimizing core wrappers in an integrated circuit to facilitate core-based testing of the integrated circuit. In some embodiments, an integrated circuit design flow is adjusted so as to increase the use of shared wrapper cells in inserted core wrappers, and to reduce the use of dedicated wrapper cells in such core wrappers, thereby improving timing and other integrated circuit design features. In these and other embodiments, the increased use of shared wrapper cells is performed even in the presence of shift registers in the integrated circuit design.