Optimizing core wrappers in an integrated circuit

    公开(公告)号:US10234504B1

    公开(公告)日:2019-03-19

    申请号:US15452526

    申请日:2017-03-07

    Abstract: According to certain aspects, the present embodiments relate to optimizing core wrappers in an integrated circuit to facilitate core-based testing of the integrated circuit. In some embodiments, an integrated circuit design flow is adjusted so as to increase the use of shared wrapper cells in inserted core wrappers, and to reduce the use of dedicated wrapper cells in such core wrappers, thereby improving timing and other integrated circuit design features. In these and other embodiments, the increased use of shared wrapper cells is performed even in the presence of shift registers in the integrated circuit design.

    IP block scan chain construction
    3.
    发明授权

    公开(公告)号:US11256839B1

    公开(公告)日:2022-02-22

    申请号:US17228282

    申请日:2021-04-12

    Abstract: A scan chain engine can determine a set number of EXTEST scan chains for the IP block and based on a predetermined maximum number of EXTEST wrapper cells per EXTEST scan chain. The scan chain engine iteratively executes partitioning on the IP block to generate a set of partitions. Each partition in the set of partitions has a number of EXTEST wrapper cells that does not exceed the maximum number of EXTEST wrapper cells per EXTEST scan chain. The scan chain engine selectively merges partitions of the set of partitions to form a set of populated partitions that each include an EXTEST wrapper cell. The number of partitions is equal to the set number of EXTEST scan chains for the IP block. The scan chain engine generates wire paths connecting EXTEST wrapper cells of each populated partition to construct the set number of EXTEST scan chains for the IP block.

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