公开(公告)号：US10234504B1

公开(公告)日：2019-03-19

申请号：US15452526

申请日：2017-03-07

Applicant: Cadence Design Systems, Inc.

Inventor： Subhasish Mukherjee ,  Jagjot Kaur ,  Vivek Chickermane ,  Susan Marie Genova

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177

Abstract: According to certain aspects, the present embodiments relate to optimizing core wrappers in an integrated circuit to facilitate core-based testing of the integrated circuit. In some embodiments, an integrated circuit design flow is adjusted so as to increase the use of shared wrapper cells in inserted core wrappers, and to reduce the use of dedicated wrapper cells in such core wrappers, thereby improving timing and other integrated circuit design features. In these and other embodiments, the increased use of shared wrapper cells is performed even in the presence of shift registers in the integrated circuit design.

公开(公告)号：US11409931B1

公开(公告)日：2022-08-09

申请号：US17203497

申请日：2021-03-16

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Jagjot Kaur ,  William Scott Gaskins

IPC: G06F30/333 ,  G06F30/30 ,  G06F30/32 ,  G06F30/396 ,  G06F119/12 ,  G01R31/3185 ,  G01R31/317

Abstract: A system for optimizing scan pipelining may include a processor and a memory. The processor may generate and insert, based on prior analysis of the physical layout of the circuit, an optimized number of pipeline stages between a first block and a second block in a hardware test design, a first scan chain including at least one pipeline stage of a head pipeline stage or a tail pipeline stage. The processor may insert a plurality of flip-flops into the first scan chain. The processor may determine at least one clock to be used for the at least one pipeline stage, using the plurality of flip-flops so as to eliminate the need of a lockup element between the at least one pipeline stage and the plurality of flip-flops. The processor may generate, based on the at least one clock, a second scan chain that connects the at least one pipeline stage and the plurality of flip-flops.

公开(公告)号：US10740515B1

公开(公告)日：2020-08-11

申请号：US16224592

申请日：2018-12-18

Applicant: Cadence Design Systems, Inc.

Inventor： Jagjot Kaur ,  Priyanka Dasgupta ,  Vivek Chickermane ,  Gopi Kudva

IPC: G06F17/50 ,  G06F30/30 ,  G01R31/317 ,  G06F30/3323 ,  G06F111/04 ,  G06F111/20

Abstract: Systems, methods, media, and other such embodiments described herein relate to insertion of test points in circuit design and associated test coverage for a circuit design. One embodiment involves a circuit design with a plurality of circuit elements and a plurality of clock gating logic elements. A first node coupled to a first circuit element is selected for insertion of a test point circuit element. Elements of the design are identified that contribute to a data state of the first node, and clock elements for these identified design elements are traced. An ungated clock input node from this trace is selected, and the clock input from this node is connected to the test point circuit element. The circuit design is then updated with this connection. In various embodiments when multiple ungated clock input nodes are identified by the trace, additional criteria are used to select among the ungated clock input nodes.

公开(公告)号：US10417363B1

公开(公告)日：2019-09-17

申请号：US15391594

申请日：2016-12-27

Applicant: Cadence Design Systems, Inc.

Inventor： Jagjot Kaur ,  Priyanka Dasgupta ,  Pratyush Aditya Kothamasu ,  Vivek Chickermane

IPC: G06F17/50 ,  G06F11/27

Abstract: Embodiments relate to methodologies for applying multibit cell merging to functional shift registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring congestion in integrated circuit designs. In embodiments, during synthesis, shift registers in a design are identified. In these and other embodiments, in identified shift registers, functional shift register flip-flops are merged into non-scan multi-bit flip-flops using a physically aware approach.